Queued interrupt mechanism with supplementary command/status/message information

• US 5,319,753 A
• Filed: 09/29/1992
• Issued: 06/07/1994
• Est. Priority Date: 09/29/1992
• Status: Expired due to Term

• Current Assignee: IXYS Intl Limited (Littelfuse Incorporated)
• Original Assignee: ZiLOG Incorporated (Littelfuse Incorporated)
• Inventors: MacKenna, Craig A., Nimishakavi, Hanumanthrao, Swami, Ravi
• Primary Examiner(s): Evans, Arthur G.
• Assistant Examiner(s): Kim, Sang Hui
• Application Number:
  US07/953,732
• Time in Patent Office: 616 Days
• Field of Search: 395/275, 395/250, 395/425, 395/725, 340/172.5, 364/230.2, 364/600, 364/601, 364/280.8
• US Class Current: 710/48
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence

Abstract

A bidirectional interrupt technique and mechanism is described for handling programmable length interrupt messages between two devices, preferably both processors, through dual, programmably defined memory queues. The technique and mechanism automatically updates a read and write address counter, a queue count register, and an interrupt count register for each direction of the flow of interrupts.

Claims

1. A circuit for passing interrupt information between a first and second device, comprising:

a memory device having a first plurality of sequentially addressed storage locations for storing items of interrupt information being passed from said first device to said second device, said first plurality of sequentially addressed storage locations having a beginning address in said sequence of addresses, an ending address in said sequence of addresses, and a size equal to said ending address minus said beginning address plus one;

a first register having an addressed storage location for storing said beginning address in said sequence of memory addresses of said first plurality of sequentially addressed storage locations; and

a second register having an addressed storage location for storing said size of said first plurality of sequentially addressed storage locations.

2. The circuit as recited in claim 1, said memory device further having a second plurality of sequentially addressed storage locations for storing items of interrupt information being passed from said second device to said first device, said second plurality of sequentially addressed storage locations having a beginning address in said sequence of addresses, an ending address in said sequence of addresses, and a size equal to said ending address minus said beginning address plus one, said circuit further comprising:

a third register having an addressed storage location for storing said beginning address in said sequence of memory addresses of said second plurality of sequentially addressed storage locations; and

a fourth register having an addressed storage location for storing said size of said second plurality of sequentially addressed storage locations.

3. The circuit as recited in claim 2 wherein said first and second devices are both processors.

4. A circuit for passing interrupt information between a first and second device, said first and second devices connected to said circuit by a system bus including an address bus, a data bus, and a control signal bus, said circuit comprising:

a memory device having a first plurality of sequentially addressed storage locations for storing items of interrupt information being passed from said first device to said second device, said first plurality of sequentially addressed storage locations having a beginning address in said sequence of addresses, an ending address in said sequence of addresses, and a size equal to said ending address minus said beginning address plus one;

a first write address counter having an addressed storage location initially storing said beginning address of said first plurality of sequentially addressed storage locations;

a first interrupt counter having an addressed storage location initially storing an interrupt count of zero;

a first queue counter having an addressed storage location initially storing an item of interrupt information count of zero; and

control logic connected to said memory device, said first write counter, said first interrupt counter, said first queue counter, and by said system bus, to said first and second devices, wherein said control logic causes an item of interrupt information received from said first device over said data bus to be stored in said first plurality of sequentially addressed storage locations, an address stored in said first write counter to be incremented to a next address in said sequence of addresses of said first plurality of sequentially addressed storage locations, and an item of interrupt information count stored in said first queue counter to be incremented by one, if said control logic receives a write signal over said control signal bus and a first or second pseudo register address over said address bus, and also causes an interrupt count stored in said first interrupt counter to be incremented by one, if said control logic receives said second pseudo register address over said address bus.

5. The circuit as recited in claim 4, said circuit further comprising a first read address counter connected to said control logic, said first read address counter having an addressed storage location initially storing said beginning address of said first plurality of sequentially addressed storage locations, wherein said control logic causes an item of interrupt information retrieved from said first plurality of sequentially addressed storage locations at an address stored in said first read address counter to be provided on said data bus, said address stored in said first read address counter to be incremented to a next address in said sequence of addresses of said first plurality of sequentially addressed storage locations, and said item of interrupt information count stored in said first queue counter to be decremented by one, if said control logic receives a read signal over said control signal bus and said first or second pseudo register address over said address bus, and also causes said interrupt count stored in said first interrupt counter to be decremented by one, if said control logic receives said second pseudo register address over said address bus.

6. The circuit as recited in claim 4, said memory device further having a second plurality of sequentially addressed storage locations for storing items of interrupt information being passed from said second device to said first device, said second plurality of sequentially addressed storage locations having a beginning address in said sequence of addresses, an ending address in said sequence of addresses, and a size equal to said ending address minus said beginning address plus one, said circuit further comprising:

a second write address counter connected to said control logic, said second write register having an addressed storage location initially storing said beginning address of said second plurality of sequentially addressed storage locations;

a second interrupt counter having an addressed storage location initially storing an interrupt count of zero; and

a second queue counter having an addressed storage location initially storing an item of interrupt information count of zero;

wherein said control logic is also connected to said second interrupt counter and said second queue counter, and causes an item of interrupt information received from said second device over said data bus to be stored in said second plurality of sequentially addressed storage locations, an address stored in said second write counter to be incremented to a next address in said sequence of addresses of said second plurality of sequentially addressed storage locations, and an item of interrupt information count stored in said second queue counter to be incremented by one, if said control logic receives a write signal over said control signal bus and a third or fourth pseudo register address over said address bus, and also causes an interrupt count stored in said second interrupt counter to be incremented by one, if said control logic receives said fourth pseudo register address over said address bus.

7. The circuit as recited in claim 6, said circuit further comprising a second read address counter connected to said control logic, said second read address counter having an addressed storage location initially storing said beginning address of said second plurality of sequentially addressed storage locations, wherein said control logic causes an item of interrupt information retrieved from said second plurality of sequentially addressed storage locations at an address stored in said second read address counter to be provided on said data bus, said address stored in said second read address counter to be incremented to a next address in said sequence of addresses of said second plurality of sequentially addressed storage locations, and said item of interrupt information count stored in said second queue counter to be decremented by one, if said control logic receives a read signal over said control signal bus and said third or fourth pseudo register address over said address bus, and also causes said interrupt count stored in said second interrupt counter to be decremented by one, if said control logic receives said fourth pseudo register address over said address bus.

8. A method of receiving interrupt information from a first device, queuing said interrupt information in a memory device, signaling a second device after said queuing, and transmitting said queued interrupt information to said second device upon request by said second device, comprising the steps of:

(a) receiving a write signal from a control signal bus, an item of interrupt information from a data bus, and a pseudo register address from an address bus, wherein said pseudo register address indicates from which device said item of interrupt information is being sent;

(b) retrieving a memory address from a first selected one of a plurality of registers in response to said write signal and said pseudo register address;

(c) causing said item of interrupt information to be stored in said memory device at said retrieved memory address;

(d) updating the memory address stored in said first selected one of said plurality of registers; and

incrementing, if said pseudo register address is a first or second pseudo register address, a queue counter containing a count of the number of items of unread interrupt information that have been passed from said first device to said second device and stored in said memory device, and also incrementing, if said pseudo register address is said second pseudo register address, an interrupt counter containing a count of the number of unread interrupts that have been initiated by said first device for said second device.

9. The method as recited in claim 8 further comprising the steps of:

(g) checking the contents of said interrupt counter, and generating and transmitting an interrupt signal to said second device if said contents are not equal to zero;

(h) receiving a read signal from said control signal bus, and a pseudo register address from said address bus;

(i) retrieving a memory address from a second selected one of said plurality of registers in response to said read signal and said pseudo register address;

(j) providing a read signal and said retrieved memory address to said memory device, and receiving an item of interrupt information from said memory device in response thereof;

(k) transmitting said received item of interrupt information to said second device;

(l) updating the memory address stored in said second selected one of said plurality of registers; and

(m) decrementing said queue counter if said pseudo register address is a third or fourth pseudo register address, and also decrementing said interrupt counter if said pseudo register address is said fourth pseudo register address.

10. The method as recited in claim 8 wherein said (d) comprises the steps of:

(d1) incrementing the memory address stored in said first selected one of said plurality of registers; and

(d2) blocking an appropriate carry bit determined from the contents of a queue size register.

11. The method as recited in claim 8 further comprising the steps of:

(g) checking the contents of said interrupt counter, and generating and transmitting an interrupt signal to said second device if said contents are not equal to zero;

(h) receiving an interrupt acknowledge signal from said second device;

(i) retrieving a memory address from a second selected one of said plurality of registers in response to said interrupt acknowledge signal;

(j) providing a read signal and said retrieved memory address to said memory device, and receiving an item of interrupt information from said memory device in response thereof;

(k) transmitting said received item of interrupt information to said second device;

(l) updating the memory address stored in said second selected one of said plurality of registers; and

(m) decrementing said queue counter if said pseudo register address is a third or a fourth pseudo register address, and also decrementing said interrupt counter if said pseudo register address is said fourth pseudo register address.