Integrated circuit I/O using high performance bus interface

• US 5,319,755 A
• Filed: 09/30/1992
• Issued: 06/07/1994
• Est. Priority Date: 04/18/1990
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): Fleming, Michael R.
• Assistant Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US07/954,945
• Time in Patent Office: 615 Days
• Field of Search: 395/325, 395/425, 395/725, 364/240.3, 364/240.1, 364/243, 364/DIG. 1, 364/935.47, 364/940.2, 364/964, 364/DIG. 2
• US Class Current: 710/104
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus for storing and retrieving data is described. The apparatus includes a circuitry for initiating data transmission, a first memory, a second memory, and a multiline bus for transferring control information, addresses, and the data. The control information includes information for selecting one of the first and second memories without using any separate memory select line. Configuration circuitry is provided for assigning a first identification value to the first memory and a second identification value to the second memory. The configuration circuitry includes a first reset line for coupling the circuitry for initiating data transmission to the first memory, a second reset line for coupling the first memory to the second memory, a first identification register for the first memory, a second identification register for the second memory, circuitry for generating a first reset signal and a second reset signal and for sending the first and second reset signals to the first identification register, circuitry for propagating the first and second reset signals from the first identification register to the second identification register, circuitry for resetting the first and second identification registers in response to the first reset signal, and circuitry for setting the first identification register to the first identification value and the second identification register to the second identification value in response to the second reset signal.

Claims

1. An apparatus for storing and retrieving data, wherein the apparatus comprises:

(A) a first memory;

(B) a second memory;

(C) a multiline bus for coupling the first and second memories and for carrying control information, addresses, and the data, wherein the multiline bus has a total number of lines less than a total number of bits in any single address, wherein the control information includes information for selecting one of the first and second memories without using any separate memory select line;

(D) a multiline transceiver bus;

(E) means for initiating data transmission coupled to the multiline transceiver bus;

(F) a transceiver for coupling the multiline transceiver bus to the multiline bus, for coupling the means for initiating data transmission to the first and second memories, and for carrying the control information, addresses, and the data, wherein the multiline transceiver bus has a total number of lines less than a total number of bits in any single address, wherein the control information includes information for selecting one of the first and second memories without using any separate memory select line;

(G) configuration means for assigning a first identification value to the first memory and a second identification value to the second memory, wherein the configuration means further comprises;

(i) a first reset line for coupling the means for initiating data transmission to the first memory;

(ii) a second reset line for coupling the first memory to the second memory;

(iii) a first identification register for the first memory, wherein the first identification register is coupled to the first reset line and the multiline bus;

(iv) a second identification register for the second memory, wherein the second identification register is coupled to the second reset line and the multiline bus;

(v) means for generating a first reset signal and a second reset signal and for sending the first reset signal and the second reset signal to the first identification register of the first memory, wherein the generating means is coupled to the first reset line and the multiline bus, wherein the generating means also generates the first identification value and the second identification value;

(vi) means for propagating the first reset signal and the second reset signal from the first identification register of the first memory to the second identification register of the second memory, wherein the propagating means is coupled to the first identification register and the second reset line;

(vii) means in each of the first and second identification registers for resetting the first and second identification registers in response to the first reset signal, wherein the resetting means receives the first reset signal in the first identification register from the first reset line and in the second identified register from the second reset line;

(viii) means in each of the first and second identification registers for setting the first identification register to the first identification value and the second identification register to the second identification value in response to the second reset signal, wherein the setting means causes the first identification register to receive the first identification value from the generating means (1) the first reset line or (2) the multiline bus when the first identification register receives the second reset signal via the first reset line, wherein the setting means causes the second identification register to receive the second identification value from the generating means via (1) the first and second reset lines or (2) the multiline bus when the second identification register receives the second reset signal via the second reset line.

2. The apparatus of claim 1 for storing and retrieving data, wherein the first memory is a dynamic random access memory and the second memory is a dynamic random access memory.

3. The apparatus of claim 1 for storing and retrieving data, wherein the means for initiating data transmission is a processing unit.

4. The apparatus of claim 1 for storing and retrieving data, wherein the means for initiating data transmission is a central processing unit.

5. The apparatus of claim 1 for storing and retrieving data, wherein the means for initiating data transmission is a direct memory access unit.

6. The apparatus of claim 1 for storing and retrieving data, wherein the means for initiating data transmission is a floating point unit.

7. The apparatus of claim 1 for storing and retrieving data, wherein the means for initiating data transmission is a master.

8. The apparatus of claim 7 for storing and retrieving data, wherein the first memory and the second memory are each a slave.

9. The apparatus of claim 1 for storing and retrieving data, further comprising a master, wherein the means for initiating data transmission, the first memory, and the second memory are each a slave, wherein the master includes the means for generating the first reset signal and the second reset signal, and wherein the master is coupled to the multiline transceiver bus.

10. The apparatus of claim 1 for storing and retrieving data, further comprising a peripheral device coupled to the multiline transceiver bus.

11. The apparatus of claim 10 for storing and retrieving data, wherein the peripheral device is an input/output interface port.

12. The apparatus of claim 10 for storing and retrieving data, wherein the peripheral device is a video controller.

13. The apparatus of claim 10 for storing and retrieving data, wherein the peripheral device is a disk controller.

14. The apparatus of claim 1 for storing and retrieving data, wherein the multiline transceiver bus is in a different plane than a plane in which the multiline bus resides.

15. The apparatus of claim 1 for storing and retrieving data, wherein the multiline bus lies in a first plane and the multiline transceiver bus lies in a second plane orthogonal to the first plane.

16. The apparatus of claim 1 for storing and retrieving data, further comprising:

a second multiline transceiver bus;

a second transceiver for coupling the second multiline transceiver bus to the multiline transceiver bus, wherein the second multiline transceiver bus carries the control information, addresses, and data, and wherein the second multiline transceiver bus has a total number of lines less than a total number of bits in any single address.

56. The apparatus of claim 5 for storing and retrieving data, wherein the low-voltage swing signals swing between an upper voltage and a lower voltage.

57. The apparatus of claim 56 for storing and retrieving data, wherein the upper voltage is approximately two volts.

58. The apparatus of claim 56 for storing and retrieving data, wherein a difference between the upper voltage and the lower voltage is approximately 500 millivolts.

17. An apparatus for storing and retrieving data for a system that includes a means for initiating data transmission, wherein the apparatus comprises:

(A) a first memory;

(B) a second memory;

(C) a multiline bus for coupling the means for initiating data transmission to the first and second memories, and for carrying control information, addresses, and the data, wherein the multiline bus has a total number of lines less than a total number of bits in any single address, wherein the control information includes information for selecting one of the first and second memories without using any separate memory select line;

(D) configuration means for assigning a first identification value to the first memory and a second identification value to the second memory, wherein the configuration means further comprises;

(i) a first reset line for coupling the means for initiating data transmission to the first memory;

(ii) a second reset line for coupling the first memory to the second memory;

(iii) a first identification register for the first memory, wherein the first identification register is coupled to the first reset line and the multiline bus;

(iv) a second identification register for the second memory, wherein the second identification register is coupled to the second reset line and the multiline bus;

(v) means for generating a first reset signal and a second reset signal and for sending the first reset signal and the second reset signal to the first identification register of the first memory, wherein the generating means is coupled to the first reset lien and the multiline bus, wherein the generating means also generates the first identification value and the second identification value;

(vi) means for propagating the first reset signal and the second reset signal from the first identification register of the first memory to the second identification register of the second memory, wherein the propagating means is coupled to the first identification register and the second reset line;

(vii) means in each of the first and second identification registers for resetting the first and second identification registers in response to the first reset signal, wherein the resetting means receives the first reset signal in the first identification register from the first reset line and in the second identification register from the second reset line;

(viii) means in each of the first and second identification registers for setting the first identification register to the first identification value and the second identification register to the second identification value in response to the second reset signal, wherein the setting means causes the first identification register to receive the first identification value from the generating means via (1) the first reset line or (2) the multiline bus when the first identification register receives the second reset signal via the first reset line, wherein the setting means causes the second identification register to receive the second identification value from the generating means via (1) the first and second reset lines or (2) the multiline bus when the second identification register receives the second reset signal via the second reset line.

18. An apparatus for storing and retrieving data, wherein the apparatus comprises:

(a) a master;

(b) a first memory;

(c) a second memory;

(d) a multiline bus for coupling the master to the first and second memories and for carrying control information, addresses, and the data, wherein the multiline bus has a total number of lines less than a total number of bits in any single address, wherein the control information includes information for selecting one of the first and second memories without using any separate memory select line;

(e) configuration means for assigning a first identification value to the first memory and a second identification value to the second memory, wherein the configuration means further comprises;

(i) a first reset line for coupling the master to the first memory;

(ii) a second reset line for coupling the first memory to the second memory;

(iii) a first identification register for the first memory, wherein the first identification register is coupled to the first reset line and the multiline bus;

(iv) a second identification register for the second memory, wherein the second identification register is coupled to the second reset line and the multiline bus;

(v) means for generating a first reset signal and a second reset signal and for sending the first reset signal and the second reset signal to the first identification register of the first memory, wherein the generating means is coupled to the first reset line and the multiline bus, wherein the generating means also generates the first identification value and the second identification value;

(vi) means for propagating the first reset signal and the second reset signal from the first identification register of the first memory to the second identification register of the second memory, wherein the propagating means is coupled to the first identification register and the second reset line;

(vii) means in each of the first and second identification registers for resetting the first and second identification registers in response to the first reset signal, wherein the resetting means receives the first reset signal from the first reset line in the first identification register and from the second reset line in the second identification register;

(viii) means in each of the first and the second identification registers for setting the first identification register to the first identification value and the second identification register to the second identification value in response to the second reset signal, wherein the setting means causes the first identification register to receive the first identification value from the generating means via (1) the first reset line or (2) the multiline bus when the first identification register receives the second reset signal via the first reset line, wherein the setting means causes the second identification register to receive the second identification value from the generating means via (1) the first and second reset lines or (2) the multiline bus when the second identification register receives the second reset signal via the second reset line.

19. The apparatus of claim 18 for storing and retrieving data, wherein the master is a central processing unit.

20. The apparatus of claim 18 for storing and retrieving data, wherein the master is a direct memory access unit.

21. The apparatus of claim 18 for storing and retrieving data, wherein the master is a floating point unit.

22. The apparatus of claim 18 for storing and retrieving data, wherein the first memory further comprises:

(A) at least one discrete memory section and

(B) a modifiable address register adapted to store memory address information that corresponds to each discrete memory section.

23. The apparatus of claim 22 for storing and retrieving data, further comprising means for the master to request the first memory to prepare for a bus transaction by sending a request packet along the bus, wherein the first memory and the master each includes (1) a means for initiating an internal phase for preparing a bus access phase of the bus transaction and (2) a bus access means to effect the bus transaction during the bus access phase, wherein the request packet comprises a sequence of bytes containing first control information and a first address, wherein the first control information includes information about the requested bus transaction and about an access time, wherein the access time corresponds to a number of bus cycles that must intervene before beginning the bus access phase, and wherein the first address points to a memory location within the discrete memory section of the first memory.

24. The apparatus of claim 23 for storing and retrieving data, wherein the first memory includes means to read the first control information.

25. The apparatus of claim 23 for storing and retrieving data, wherein the first control information comprises an op code.

26. The apparatus of claim 25 for storing and retrieving data, wherein the first memory further comprises:

(A) a sense amplifier;

(B) means for transferring a data block during the bus transaction;

(C) response means, wherein the op code instructs the first memory to activate the response means, wherein the response means comprises means to

(1) initiate the data block transfer;

(2) select a size of the data block;

(3) select a time to initiate the data block transfer;

(4) access a control register;

(5) precharge the sense amplifier before and after the data block transfer is complete;

(6) hold data the sense amplifier after the data block transfer is complete; and

(7) select normal and page-mode access.

27. The apparatus of claim 26 for storing and retrieving data, wherein the data block transfer selectively comprises a read from and write to the first memory.

28. The apparatus of claim 23 for storing and retrieving data, further comprising means for the master to send to a specific one of the first and second memories via the bus a request packet containing first control information by including in the request packet an identification number unique to one of the first and second memories.

29. The apparatus of claim 23 for storing and retrieving data, further comprising means for the master to send to both the first and second memories via the bus a request packet containing first control information by including in the request packet a special identification number that is recognized by both the first and second memories.

30. The apparatus of claim 23 for storing and retrieving data, wherein the bus transaction is a data block transfer, and wherein the first control information further comprises a block-size value that specifies a size of the block of data to be transferred.

31. The apparatus of claim 23 for storing and retrieving data, further comprising means for generating and controlling a plurality of bus cycles during which the bus carries the control information, addresses, and data, and wherein alternate bus cycles are designated odd cycles and even cycles, respectively, and wherein the request packet begins only on an even cycle.

32. The apparatus of claim 22 for storing and retrieving data, wherein the first memory is a dynamic random access memory further comprising:

(A) a plurality of sense amplifiers;

(B) means to hold the sense amplifiers in an unmodified state after a selective read and write operation, wherein the first memory is left in page mode;

(C) means to precharge the sense amplifiers;

(D) means for selecting whether to (1) precharge the sense amplifiers or (2) hold the sense amplifiers in an unmodified state.

33. An apparatus for storing and retrieving data, wherein the apparatus comprises:

(a) means for initiating data transmission;

(b) a first memory;

(c) a second memory;

(d) a multiline bus for coupling the means for initiating data transmission to the first and second memories and for carrying control information, addresses, and the data, wherein the multiline bus has a total number of lines less than a total number of bits in any single address, wherein the control information includes information for selecting one of the first and second memories without using any separate memory select line;

(e) configuration means for assigning a first identification value to the first memory and a second identification value to the second memory, wherein the configuration means further comprises;

(i) a first reset line for coupling the means for initiating data transmission to the first memory;

(ii) a second reset line for coupling the first memory to the second memory;

(iii) a first identification register for the first memory, wherein the first identification register is coupled to the first reset line and the multiline bus;

(iv) a second identification register for the second memory, wherein the second identification register is coupled to the second reset line and the multiline bus;

(v) means for generating a first reset signal and a second reset signal and for sending the first reset signal and the second reset signal to the first identification register of the first memory, wherein the generating means is coupled to the first reset line and the multiline bus, wherein the generating means also generates the first identification value and the second identification value;

(vi) means for propagating the first reset signal and the second reset signal from the first identification register of the first memory to the second identification register of the second memory, wherein the propagating means is coupled to the first identification register and the second reset line;

(vii) means in each of the first and second identification registers for resetting the first and second identification registers in response to the first reset signal, wherein the resetting means receives the first reset signal from the first reset line in the first identification register and from the second reset line in the second identification register;

(viii) means in each of the first and second identification registers for setting the first identification register to the first identification value and the second identification register to the second identification value in response to the second reset signal, wherein the setting means causes the first identification register to receive the first identification value from the generating means via (1) the first reset line or (2) the multiline bus when the first identification register receives the second reset signal via the first reset line, wherein the setting means causes the second identification register to receive the second identification value from the generating means via (1) the first and second reset lines or (2) the multiline bus when the second identification register receives the second reset signal via the second reset line.

34. The apparatus of claim 33 for storing and retrieving data, wherein the means for setting the first identification register to the first identification value and the second identification register to the second identification value comprises circuitry for retrieving the first and second identification values from the multiline bus in response to the second reset signal.

35. The apparatus of claim 33 for storing and retrieving data, wherein the means for setting the first identification register to the first identification value and the second identification register to the second identification value comprises circuitry for retrieving the first and second identification values from the second reset signal.

36. The apparatus of claim 33 for storing and retrieving data, wherein the means propagating the first and second reset signals comprises a shift register.

37. The apparatus of claim 33 for storing and retrieving data, wherein the first memory is a dynamic random access memory and the second memory is a dynamic random access memory.

38. The apparatus of claim 33 for storing and retrieving data, wherein the means for initiating data transmission is a processing unit.

39. The apparatus of claim 33 for storing and retrieving data, wherein the means for initiating data transmission is a central processing unit.

40. The apparatus of claim 33 for storing and retrieving data, wherein the means for initiating data transmission is a direct memory access unit.

41. The apparatus of claim 33 for storing and retrieving data, wherein the means for initiating data transmission is a floating point unit.

42. The apparatus of claim 33 for storing and retrieving data, wherein the means for initiating data transmission is a master.

43. The apparatus of claim 42 for storing and retrieving data, wherein the first memory and the second memory are each a slave.

44. The apparatus of claim 42 for storing and retrieving data, wherein

(A) the first memory includes:

(1) at least one discrete memory section;

(2) a modifiable address register;

(B) the master includes;

(1) means for selecting and testing each discrete memory section of the first memory;

(2) means for avoiding a nonfunctional discrete memory section, wherein the avoiding means is responsive to the means for selecting and testing, wherein the avoiding means stores in the modifiable address register address information corresponding to each discrete memory section.

45. The apparatus of claim 33 for storing and retrieving data, wherein the first memory is a master.

46. The apparatus of claim 33 for storing and retrieving data, wherein the means for initiating data transmission and the first memory are each a master.

47. The apparatus of claim 33 for storing and retrieving data, further comprising a master, wherein the means for initiating data transmission, the first memory, and the second memory are each a slave, and wherein the means for generating the first and second reset signals reside within the master.

48. The apparatus of claim 33 for storing and retrieving data, wherein the means for initiating data transmission comprises a first master and wherein the means for generating the first and second reset signals resides within the means for initiating data transmission.

49. The apparatus of claim 48 for storing and retrieving data, wherein the means for initiating data transmission further comprises means for assigning a first master identification value to the means for initiating data transmission.

50. The apparatus of claim 49 for storing and retrieving data, further comprising:

a second master;

means for the first master to assign a second master identification value to the second master.

51. The apparatus of claim 33 for storing and retrieving data, wherein

the first memory includes a first memory type register and a first access time register;

the second memory includes a second memory type register and a second access time register.

52. The apparatus of claim 51 for storing and retrieving data, wherein the means for initiating data transmission is a master that comprises:

means for reading the first memory type register and determining a memory type of the first memory;

means for reading the first access time register and determining an access time of the first memory;

means for reading the second memory type register and determining a memory type of the second memory;

means for reading the second access time register and determining an access time of the second memory.

53. The apparatus of claim 33 for storing and retrieving data, wherein

(A) each line of the multiline bus is a transmission line and

(B) the control information, addresses, and data carried by the bus are all low-voltage swing signals.

54. The apparatus of claim 53 for storing and retrieving data, wherein each transmission line is terminated.

55. The apparatus of claim 53 for storing and retrieving data, wherein

(A) the first memory includes a first current mode driver coupled to a line of the multibit bus.;

(B) the second memory includes a second current mode driver coupled to the line of the multibit bus.

59. The apparatus of claim 53 for storing and retrieving data, wherein the first memory further comprises

(A) two input receivers coupled to a line of the multibit bus;

(B) selection means for maximizing bandwidth by selecting the two input receivers alternately to sense the low voltage swing signals.