Polling of I/O device status comparison performed in the polled I/O device

• US 5,319,785 A
• Filed: 10/16/1992
• Issued: 06/07/1994
• Est. Priority Date: 06/28/1991
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Thaller, Kurt M.
• Primary Examiner(s): Shaw, Dale M.
• Assistant Examiner(s): Barry, Lance Leonard
• Application Number:
  US07/962,624
• Time in Patent Office: 599 Days
• Field of Search: 340/500, 340/505, 340/506, 340/825.06, 340/825.07, 340/825.08, 364/200 MS, 364/900 MS, 395/200, 395/325, 395/275, 395/725, 371/16.3, 371/62
• US Class Current: 710/15
• CPC Class Codes: G06F 13/126 and has means for transferring I/O instructions and statuses between control unit and main processor
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053

Abstract

A method and apparatus for polling a status register selectively delays the returning of status data in the status register. Prior to polling, a match register is loaded via a system bus with a desired status. Status data is presented to the system bus when the status data is the same as the desired status. The features of the invention also permit the masking of selective bits of the status register during the comparison of the status data with the desired status. A mode register selectively inhibits the delayed presentation, and a timer ensures that status data is presented to the system bus within a predetermined interval even if the status data is not the same as the desired status.

Claims

1. A method for a central processing unit (CPU) to obtain from an input/output (I/O) device the contents of a status register therein indicating the status thereof, comprising the steps of:

transferring from said CPU to said I/O device expected status data corresponding to a predetermined status to be attained by said I/O device upon the occurrence of an expected event;

storing said expected status data in a match register in said I/O device for use during a subsequent polling operation;

issuing from said CPU to said I/O device a request to read said status register as part of said polling operation;

comparing the contents of said status register to the contents of said match register to determine whether said event has occurred, the occurrence of said event being indicated by a match therebetween; and

returning the contents of said status register to said CPU in response to said request upon an indication of a match in said comparing step.

2. A method according to claim 1, further comprising the steps of:

transferring from said CPU to said I/O device a mask pattern to be used in said comparing step, said mask pattern having at least one bit set to one binary logic level to indicate that a corresponding bit in said status register is to be used in said comparing step, the remaining bits of said mask pattern being set to the other binary logic level to indicate that corresponding bits in said status register are to be ignored in said comparing step;

storing said mask pattern in a mask register in said I/O device for use during said polling operation; and

forcing the indication of a match in said comparing step for those bits of said status register corresponding to those bits of said mask register having said other binary logic level.

3. A method according to claim 1, further comprising the steps of:

transferring a mode data bit from said CPU to said I/O device prior to said polling operation, said mode data bit being set to one binary logic level to indicate that the contents of said status register should be returned to said CPU upon the receipt of said request by said I/O device without regard for a match in said comparing step, said mode data bit being otherwise set to the other binary logic level;

storing said mode data bit in a mode register in said I/O device for use during said polling operation;

returning the contents of said status register to said CPU immediately upon the receipt of said request by said I/O device without regard for a match in said comparing step if the bit stored in said mode register has said one binary logic value; and

returning the contents of said status register to said CPU in response to said request upon an indication of a match in said comparing step if the bit stored in said mode register has the other binary logic value.

4. A method according to claim 1, further comprising the steps of:

initializing a timer in said I/O device used to determine whether the duration between the receipt of said request by said I/O device and the return of the contents of said status register to said CPU exceeds a predetermined maximum duration;

starting said timer upon receipt of said request by said I/O device; and

returning the contents of said status register to said CPU upon the expiration of said time if by that time a match has not been indicated in said comparing step.

5. A computer system, comprising:

a central processing unit (CPU);

a status register coupled to said CPU whose contents indicate the status of an associated input/output (I/O) device to be polled by said CPU;

a match register coupled to said CPU to be written therefrom with expected status data corresponding to a predetermined status to be attained by said I/O device upon the occurrence of an expected event;

a comparator coupled to said status register and said match register to indicate whether the contents thereof match;

means for receiving from said CPU a request to read said status register to determine whether said event has occurred; and

means for returning the contents of said status register to said CPU in response to said request upon an indication of a match by said comparator.

6. A computer system according to claim 5, further comprising:

a mask register coupled to said CPU to receive therefrom a mask pattern, said mask pattern having at least one bit set to one binary logic level to indicate that a corresponding bit in said status register is to be used by said comparator, the remaining bits of said mask pattern being set to the other binary logic level to indicate that corresponding bits in said status register are to be ignored by said comparator, said mask register being coupled to said comparator to provide said mask pattern thereto; and

wherein said comparator has means for forcing the indication of a match for those bits of said status register corresponding to those bits of said mask register having said other binary logic level.

7. A computer system according to claim 5, further comprising:

a mode register coupled to said CPU to receive therefrom a mode data bit, said mode data bit being set to one binary logic level to indicate that the contents of said status register should be returned to said CPU upon the receipt of said request by said I/O device without regard for a match indication by said comparator, said mode data bit being otherwise set to the other binary logic level;

means for returning the contents of said status register to said CPU upon the receipt of said request by said I/O device without regard for a match indication by said comparator if the bit stored in said mode register has said one binary logic value; and

means for returning the contents of said status register to said CPU in response to said request an indication of a match by said comparator if the bit stored in said mode register has the other binary logic value.

8. A computer system according to claim 5, further comprising:

a timer coupled to said receiving means, said comparator, and said returning means to determine whether the duration between the receipt of said request by said I/O device and the return of the contents of said status register to said CPU exceeds a predetermined maximum duration;

means for starting said timer upon receipt of said request by said I/O device; and

means for returning the contents of said status register to said CPU upon the expiration of said timer if by that time a match has not been indicated by said comparator.