Non-volatile semiconductor memory device having thin film memory transistors stacked over associated selecting transistors

• US 5,321,286 A
• Filed: 11/19/1992
• Issued: 06/14/1994
• Est. Priority Date: 11/26/1991
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Koyama, Shoji, Inoue, Tatsuro
• Primary Examiner(s): JACKSON JR, JEROME
• Application Number:
  US07/978,899
• Time in Patent Office: 572 Days
• Field of Search: 257/315, 257/349, 257/66, 257/67, 257/71, 257/57, 257/314, 365/185
• US Class Current: 257/315
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/43 comprising only one type of peripheral transistor

Abstract

A electrically erasable and programmable read only memory device has a memory cell array implemented by a plurality of floating gate type memory transistors, and each of the floating gate type memory transistors is implemented by a thin film field effect transistor with a floating gate electrode formed on a relatively thick insulating film covering a major surface of a semiconductor substrate so that the biasing conditions and crystal defects do not have any influence on the floating gate type memory transistor.

Claims

1. A non-volatile semiconductor memory device fabricated on a semiconductor substrate, comprising:

a) a first selecting means implemented by a first bulk transistor comprising a-1) source and drain regions formed in surface portions of said semiconductor substrate, and spaced from each other by a first channel region, a-2) a first gate insulating film formed on said first channel region, and a-3) a first gate electrode formed on said first gate insulating film;

b) a second selecting means coupled with one of said source and drain regions of said first bulk transistor, and implemented by a plurality of second bulk transistors coupled in series, each of said plurality of second bulk transistors comprising b-1) source and drain regions formed in other surface portions of said semiconductor substrate, and spaced from each other by a second channel region, b-2) a second gate insulating film formed on said second channel region, and b-3) a second gate electrode formed on said second gate insulating film, a-4) a second gate insulating film;

c) a first inter-level insulating film covering said first selecting means and said second selecting means;

d) a lower memory cell sub-array fabricated on said first inter-level insulating film, and implemented by a plurality of floating gate type first thin film memory transistors coupled in series and respectively paired with said plurality of second bulk transistors, each of said floating gate type first thin film transistors comprising d-1) source and drain regions formed in a first semiconductor film extending over said first inter-level insulating film, and spaced apart from each other by a third channel region, said source and drain regions of said floating gate type thin film memory transistor being respectively held in contact with said source and drain regions of second bulk transistor paired therewith, d-2) a third gate insulating film covering said third channel region, d-3) a first floating gate electrode formed on said third gate insulating film, d-4) a fourth gate insulating film covering said first floating gate electrode, and d-5) a first control gate electrode formed on said fourth gate insulating film;

e) a second inter-level insulating film covering said lower memory cell sub-array;

f) a third selecting means coupled with said one of said source and drain regions of said first bulk transistor, and implemented by a plurality of thin film selecting transistors coupled in series, each of said plurality of thin film selecting transistors comprising f-1) source and drain regions formed in a second semiconductor film extending on said second inter-level insulating film, and spaced apart from each other by a fourth channel region, f-2) a fifth gate insulating film formed on said fourth channel region, and f-3) a third gate electrode formed on said fifth gate insulating film;

g) a third inter-level insulating film covering said third selecting means;

h) an upper memory cell sub-array fabricated on said third inter-level insulating film, and implemented by a plurality of floating gate type second thin film memory transistors coupled in series and respectively paired with said plurality of thin film selecting transistors, each of said floating gate type second thin film transistors comprising h-1) source and drain regions formed in a third semiconductor film extending over said third inter-level insulating film, and spaced apart from each other by a fifth channel region, said source and drain regions of said floating gate type second thin film memory transistor being respectively held in contact with said source and drain regions of said thin film selecting transistor paired therewith, h-2) a sixth gate insulating film covering said fifth channel region, h-3) a second floating gate electrode formed on said sixth gate insulating film, h-4) a seventh gate insulating film covering said second floating gate electrode, and h-5) a second control gate electrode formed on said seventh gate insulating film;

i) a fourth inter-level insulating film covering said upper memory cell sub-array, at least one contact hole projecting through said first, second, third and fourth inter-level insulating films for exposing the other of said source and drain regions of said first bulk transistor; and

j) at least one bit line extending on said fourth inter-level insulating film, and penetrating said at least one contact hole so as to be held in contact with said other of said source and drain regions of said first bulk transistor.