Semiconductor device wherein n-channel MOSFET, p-channel MOSFET and nonvolatile memory cell are formed in one chip

• US 5,321,287 A
• Filed: 04/06/1993
• Issued: 06/14/1994
• Est. Priority Date: 10/06/1989
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hanada, Naoki, Uemura, Teruo
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/043,533
• Time in Patent Office: 434 Days
• Field of Search: 257/316, 257/371, 257/377, 257/326
• US Class Current: 257/316
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor

Abstract

An n-channel MOSFET, a p-channel MOSFET and a nonvolatile memory cell are provided for the same semiconductor substrate. The nonvolatile memory cell is formed on the semiconductor substrate, the n-channel MOSFET is formed in a p-type well region of the semiconductor substrate, and the p-channel MOSFET is formed in an n-type well region of the semiconductor substrate.

Claims

1. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type having a major surface region, said substrate having an impurity concentration of p₁ ;

a first well region of the first conductivity type in the major surface region of said substrate, said first well region having an impurity concentration of p₂, said impurity concentrations p₁ and p₂ having a relationship expressed by p₁ <

p₂ ;

a second well region of a second conductivity type in the major region of said substrate;

an isolation region in the major surface region of said substrate, the isolation region having first, second and third element regions in said substrate, said first well region, said second well region, and said first element region comprising a memory cell region, and said second and third element regions comprising a peripheral circuit region;

a first insulating layer on said first element region;

a floating gate electrode on said first insulating layer;

a second insulating layer on said floating gate electrode;

third and fourth insulating layers on said second and third element regions, respectively, said third and fourth insulating layer being portions of a common layer;

a control gate electrode on said second insulating layer;

first and second gate electrodes on said third and fourth insulating layers, respectively, said first gate electrode and said second gate electrode being of material like that of said control gate electrode;

first and second active regions of a memory cell transistor of the second conductivity type in said first element region, said first and second active regions containing a first impurity of the second conductivity type;

third and fourth active regions of an insulated gate FET of the second conductivity type provided in said second element region, said third and fourth active regions containing said first impurity of the second conductivity type;

fifth and sixth active regions of an insulated gate FET of the first conductivity type provided in said third element region, said fifth and sixth active regions containing a second impurity of the first conductivity type;

a fifth insulating layer provided over the major surface of said semiconductor substrate; and

a wiring provided on said fifth insulating layer so as to be electrically connected to at least one of said first to sixth active regions.

2. The semiconductor device according to claim 1, wherein said first conductivity type is p-type, and said second conductivity type is n-type.

3. The semiconductor device according to claim 1, wherein said first active region forms a source region of said memory cell transistor, said second active region forms a drain region of said memory cell transistor, said third active region forms a source region of said insulated gate FET of the second conductivity type, said fourth active region forms a drain region of said insulated gate FET of the second conductivity type, said fifth active region forms a source region of said insulated gate FET of the first conductivity type, and said sixth active region forms a drain region of said insulated gate FET of the first conductivity type.

4. The semiconductor device according to claim 1, wherein said first and second active regions have an impurity concentration of p₃, and said third and fourth active regions have an impurity concentration of p₄, said impurity concentrations p₃ and p₄ having a relationship expressed by p₃ <

p₄.

5. The semiconductor device according to claim 1, wherein said second insulating film comprises a laminated film of a thermal oxide layer and a nitride layer.