Vertical MOSFET having trench covered with multilayer gate film

• US 5,321,289 A
• Filed: 10/21/1993
• Issued: 06/14/1994
• Est. Priority Date: 10/22/1992
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Matsuda, Noburo, Baba, Yoshiro, Yanagiya, Satoshi, Hiraki, Shunichi
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US08/139,142
• Time in Patent Office: 236 Days
• Field of Search: 257/330-334
• US Class Current: 257/331
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A vertical MOSFET includes a trench whose inner surface is covered with an insulating layer having a multilayer structure. In order to reduce a change in a gate threshold voltage, and equivalent silicon dioxide thickness of the gate insulating layer and a radius of curvature of an upper corner of the trench are provided such that a dielectric breakdown electric field strength of the gate insulating layer at the upper corner is in the range of 2.5 MV/cm to 5.0 MV/cm.

Claims

1. A vertical MOS semiconductor device comprising:

a semiconductor substrate of a first conductivity type including a first semiconductor layer of said first conductivity type;

a second semiconductor layer of a second conductivity type formed in said first semiconductor layer to provide a channel;

a third semiconductor layer of said first conductivity type formed in said second semiconductor layer;

a trench formed in said third semiconductor layer so as to reach said first semiconductor layer;

a gate insulating layer having a multilayer structure and covering a surface of said trench; and

a gate electrode layer provided on said gate insulating layer so as to fill said trench therewith;

wherein

an equivalent silicon dioxide thickness of said gate insulating layer and a radius of curvature of an upper corner of said trench are provided so that a dielectric breakdown electric field strength of said gate insulating layer at said upper corner is in the range of 2.5 MV/cm to 5.0 MV/cm.

2. The vertical MOS semiconductor device according to claim 1, wherein said gate insulating layer is comprised of a first film of silicon dioxide, a second film of silicon nitride and a third film of silicon dioxide.

3. The vertical MOS semiconductor device according to claim 1, wherein said equivalent silicon dioxide thickness t_ox of said gate insulating layer is given by 1.4≦

t_ox /a≦

6.0 when said radius of curvature of said upper corner of said trench is given by a.

4. The vertical MOS semiconductor device according to claim 1, wherein a relationship between said radium of curvature a of said upper corner of said trench and a radium of curvature b of said insulating layer at said upper corner is given by 2.4≦

b/a≦

7.0.

5. The vertical MOS semiconductor device according to claim 1, wherein a first ohmic contact serving as a drain electrode is provided on said semiconductor substrate.

6. The vertical MOS semiconductor device according to claim 1, wherein a second ohmic contact serving as a source electrode is provided on said third semiconductor layer so as to overlap said second semiconductor layer.