Method for inspecting semiconductor devices

• US 5,321,354 A
• Filed: 05/18/1992
• Issued: 06/14/1994
• Est. Priority Date: 07/23/1990
• Status: Expired due to Term

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Shimizu, Toshio, Ooshima, Yoshimasa, Kumazawa, Fumiaki, Iida, Katsuya
• Primary Examiner(s): Karlsen, Ernest F.
• Application Number:
  US07/842,121
• Time in Patent Office: 757 Days
• Field of Search: 324/158 R, 324/73.1, 371/21.1, 371/21.4, 371/25.1, 371/27
• US Class Current: 324/762.09
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G06F 11/2273 Test methods

Abstract

A method for detecting the quality of a semiconductor device using a static current that flows in a state wherein internal elements are fixed, the semiconductor device has internal elements, such as MISFETs and complementary MISFETs in particular. By using a pattern group that controls the state of nodes of the internal elements or ON/OFF and other states of MISFETs that comprise the internal elements, as a test pattern group used for this inspection, faults involving long range reliability in addition to degenerate faults and those faults detected using conventional fault simulation may be detected. In the inspection method based on static current, observability of faults at output terminals need not be taken into consideration, so that the number of patterns in the test pattern group used for inspection may be less and may be easily created.

Claims

1. A method for inspecting a semiconductor device having at least one functional cell including a plurality of internal elements, said method comprising the steps of:

applying patterns from a static current inspecting pattern group to the semiconductor device, so as to control and turn each of said internal elements into an observable state in which a static current flows in said functional cell in response to at least one fault in said functional cell, said static current inspecting pattern group including patterns suitable for measuring static current;

measuring static current after applying said patterns; and

comparing said measured static current with a predetermined value to determine whether the semiconductor device is defective.

2. The method for inspecting a semiconductor device according to claim 1, wherein said static current inspecting pattern group comprises an input value adjusted pattern group whose input values are adjusted based on circuit information for said functional cell so that at least one internal element is controlled and turned into an observable state.

3. The method for inspecting a semiconductor device according to claim 1, wherein said static current inspecting pattern group comprises a retrieved pattern group which is extracted from patterns included in a larger group of inspecting patterns, said retrieved pattern group including patterns that can control and turn at least one internal element into an observable state.

4. The method for inspecting a semiconductor device according to claim 1, wherein said static current inspecting pattern group comprises a first optimized inspecting pattern group which is extracted from patterns that can control and turn at least one internal element into an observable state, said first optimized inspecting pattern group including patterns that can control and turn specific internal elements into observable states, with said specific internal elements being least likely to be turned into observable states.

5. The method for inspecting a semiconductor device according to claim 1, wherein said static current inspecting pattern group comprises a second optimized inspecting pattern group which is extracted from patterns that can control and turn at least one internal element into an observable state, said second optimized inspecting pattern group including patterns that can control and turn a larger number of internal elements into observable states.

6. The method for inspecting a semiconductor device according to claim 5, wherein said functional cell further includes nodes for interconnecting said internal elements, and wherein said static current inspecting pattern group further comprises a node control pattern group that includes patterns that can control and turn said nodes into observable states for controlling and turning said internal elements into observable states.

7. The method for inspecting a semiconductor device according to claim 6, wherein said internal elements comprises transistors and said static current inspecting pattern group further comprises a transistor control pattern group that includes patterns that can control and turn said transistors into observable states by controlling specific ON and OFF states for said transistors.

8. The method of claim 7, wherein said transistors comprises MISFETs.

9. The method of claim 1, wherein said functional cell further includes nodes for interconnecting said internal elements, and wherein said static current inspecting pattern group further comprises a node control pattern group that includes patterns that can control and turn said nodes into observable states for controlling and turning said internal elements into observable states.

10. The method of claim 1, wherein said internal elements comprises transistors and said static current inspecting pattern group further comprises a transistor control pattern group that includes patterns that can control and turn said transistors into observable states by controlling specific ON and OFF states for said transistors.

11. The method for inspecting a semiconductor device according to claim 10, wherein said transistor control pattern group comprises a first optimized inspecting pattern group which is extracted from patterns that can control and turn at least one transistor into an observable state, said first optimized inspecting pattern group including patterns that can control and turn specific transistors into observable states, with said specific transistors being least likely to be turned into observable states.

12. The method for inspecting a semiconductor device according to claim 11, wherein said transistor control pattern group further comprises a second optimized inspecting pattern group which is extracted from the patterns that can control and turn at least one transistor into an observable state, said second optimized inspecting pattern group including patterns that can control and turn a larger number of transistors into observable states, so that a minimum number of patterns are extracted and included in said transistor control pattern group.

13. The method for inspecting a semiconductor device according to claim 10, wherein said node control pattern group comprises a second optimized inspecting pattern group which is extracted from patterns that can control and turn at least one transistor into an observable state, said second optimized inspecting pattern group including patterns that can control and turn a larger number of transistors into observable states.

14. The method for inspecting a semiconductor device according to claim 9, wherein said node control pattern group comprises a first optimized inspecting pattern group which is extracted from patterns that can control and turn at least one node into an observable state, said first optimized inspecting pattern group including patterns that can control and turn specific nodes into observable states, with said specific nodes being least likely to be turned into observable states.

15. The method for inspecting a semiconductor device according to claim 14, wherein said node control pattern group further comprises a second optimized inspecting pattern group which is extracted from the patterns that can control and turn at least one node into an observable state, said second optimized inspecting pattern group including patterns that can control and turn a larger number of nodes into observable states, so that a minimum number of patterns are extracted and included in said node control pattern group.

16. The method for inspecting a semiconductor device according to claim 9, wherein said node control pattern group comprises a second optimized inspecting pattern group which is extracted from patterns that can control and turn at least one node into an observable state, said second optimized inspecting pattern group including patterns that can control and turn a larger number of nodes into observable states.

17. The method for inspecting a semiconductor device according to claim 4, wherein said static current inspecting pattern group further comprises a second optimized inspecting pattern group which is extracted from the patterns that can control and turn at least one internal element into an observable state, said second optimized inspecting pattern group including patterns that can control and turn a larger number of internal elements into observable states, so that a minimum number of patterns are extracted and included in said static current inspecting pattern group.

18. The method for inspecting a semiconductor device according to claim 6, wherein said node control pattern group comprises a first optimized inspecting pattern group which is extracted from patterns that can control and turn at least one node into an observable state, said first optimized inspecting pattern group including patterns that can control and turn specific nodes into observable states, with said specific nodes being least likely to be turned into observable states.

19. The method for inspecting a semiconductor device according to claim 18, wherein said node control pattern group further comprises a second optimized inspecting pattern group which is extracted from the patterns that can control and turn at least one node into an observable state, said second optimized inspecting pattern group including patterns that can control and turn a larger number of nodes into observable states, so that a minimum number of patterns are extracted and included in said node control pattern group.

20. The method for inspecting a semiconductor device according to claim 6, wherein said node control pattern group comprises a second optimized inspecting pattern group which is extracted from patterns that can control and turn at least one node into an observable state, said second optimized inspecting pattern group including patterns that can control and turn a larger number of nodes into observable states.

21. The method for inspecting a semiconductor device according to claim 7, wherein said transistor control pattern group comprises a first optimized inspecting pattern group which is extracted from patterns that can control and turn at least one transistor into an observable state, said first optimized inspecting pattern group including patterns that can control and turn specific transistors into observable states, with said specific transistors being least likely to be turned into observable states.

22. The method for inspecting a semiconductor device according to claim 21, wherein said transistor control pattern group further comprises a second optimized inspecting pattern group which is extracted from the patterns that can control and turn at least one transistor into an observable state, said second optimized inspecting pattern group including patterns that can control and turn a larger number of transistors into observable states, so that a minimum number of patterns are extracted and included in said transistor control pattern group.

23. The method for inspecting a semiconductor device according to claim 7, wherein said node control pattern group comprises a second optimized inspecting pattern group which is extracted from patterns that can control and turn at least one transistor into an observable state, said second optimized inspecting pattern group including patterns that can control and turn a larger number of transistors into observable states.