Serial data interface circuit dealing with a plurality of receiving modes
First Claim
1. A serial interface circuit comprising:
- an input terminal supplied with serial data,a first shift register fetching and shifting data at said input terminal in synchronism with a clock signal,selector means for selecting said input terminal in a first mode and an output of said first shift register in a second mode,a second shift register fetching and shifting data at an output of said selector means in synchronism with said clock signal, said first and second shift registers having a set of parallel output nodes from which first and second data are derived, respectively,a set of first output terminals,a set of second output terminals,first transferring means for transferring said first and second data to said first and second output terminals in said second mode, andsecond transferring means for transferring one of said first and second data to one of said first and second output terminals in said first mode.
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Accused Products
Abstract
A serial interface circuit for performing operations in a plurality of modes is disclosed, which includes an input terminal supplied with a serial data, a first shift register fetching and shifting data at the input terminal in synchronism with a clock signal, a selector for selecting the input terminal in a first mode and an output of the first shift register in a second mode, a second shift register fetching and shifting data at an output of the selector, a set of first output terminals, a set of second output terminals, and an output control circuit outputting first data derived in parallel from the first shift register and second data derived in parallel from the second shift register to the first and second output terminals in the second mode and one of the first and second data to one of the first and second output terminals in the first mode. The respective operations in the first and second modes are thus performed. The output control is favorably incorporated with a bit order reversing function.
22 Citations
9 Claims
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1. A serial interface circuit comprising:
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an input terminal supplied with serial data, a first shift register fetching and shifting data at said input terminal in synchronism with a clock signal, selector means for selecting said input terminal in a first mode and an output of said first shift register in a second mode, a second shift register fetching and shifting data at an output of said selector means in synchronism with said clock signal, said first and second shift registers having a set of parallel output nodes from which first and second data are derived, respectively, a set of first output terminals, a set of second output terminals, first transferring means for transferring said first and second data to said first and second output terminals in said second mode, and second transferring means for transferring one of said first and second data to one of said first and second output terminals in said first mode. - View Dependent Claims (2, 3, 4)
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- 5. A serial interface circuit comprising an input terminal supplied with serial data, a first shift register fetching and shifting data at said input terminal in synchronism with a clock signal, a selector for selecting said input terminal in a first mode and an output of said first shift register in a second mode, a second shift register fetching and shifting data at an output of said selector, said first and second shift registers having a set of parallel output nodes from which first and second data are derived, respectively, a set of first output terminals, a set of second output terminals, first transferring means for transferring said first and second data to said first and second output terminals with reversing bit orders of said first and second data, and second transferring means for transferring one of a said first and second data to one of said first and second output terminals with reversing the bit order of said one of said first and second data.
- 7. A serial interface circuit comprising an input terminal supplied with serial data, a first shift register fetching and shifting data at said input terminal in synchronism with a clock signal, a selector for selecting said input terminal in a first and a second mode and for selecting an output of said first shift register in a third and a fourth mode, a second shift register fetching and shifting a data at an output of said selector, said first and second shift registers having a set of parallel output nodes from which first and second data are derived, respectively, a set of first output terminals, a set of second output terminals, first transferring means for transferring said first and second data to said first and second output terminals without reversing bit orders of said first and second data in said third mode, second transferring means for transferring said first and second data to said first and second output terminals with reversing the bit orders of said first and second data in said fourth mode, third transferring means for transferring one of said first and second data to one of said first and second output terminals without reversing the bit order of said one of said first and second data in said first mode, and fourth transferring means for transferring said one of said first and second data to said one of said first and second output terminals with reversing the bit order of said one of said first and second data in said second mode.
Specification