Serial video processor

• US 5,321,510 A
• Filed: 06/05/1992
• Issued: 06/14/1994
• Est. Priority Date: 11/13/1989
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hyslop, Adin, Childers, Jimmie D.
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): Harvey, David E.
• Application Number:
  US07/895,146
• Time in Patent Office: 739 Days
• Field of Search: 358/21 R, 358/160, 382/41, 382/42, 324/73 R, 364/604
• US Class Current: 348/571
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: H04N 5/14 Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00

Abstract

A system for real-time digital processing of a video signal using a large number of one-bit serial processor elements each of which operates on one pixel of a horizontal scan. The video signal is converted to digital by an A-to-D converter, and stored in a set of input registers, one register for each processor element. All of these input registers are loaded during a horizontal scan, as the input registers are addressed in sequence by a commutator. Each processor element includes a one-bit binary adder, a set of one-bit registers, and two one-bit wide data memories of a size to store data from several scans. The processor elements are all controlled in common by a sequencer, a state machine or a processor. The processed video data is transferred to an output register for each processor element, from which it is converted to a video signal by a D-to-A converter. A frame memory may be used to save a processed frame for use in convolving the next frame; the input of the frame memory is taken at the output registers, and the frame memory output is applied to the input registers.

Claims

1. A serial video processor system for real-time processing of raster-scanned video, comprising:

an input for receiving digitized, multi-bit video data;

a plurality of serial video processors, each video processor having;

an input register connected to receive said multi-bit video data from said input;

an output register connected to transfer multi-bit processed data from the video processor;

first and second random-access memories each having data inputs and outputs connected to said input and output registers and each having an address input;

a serial ALU having a plurality of one-bit registers and multiplexer means to connect inputs and outputs of each said registers to data inputs and outputs of said first and second random-access memories, the multiplexer means also connecting inputs and outputs of some of the registers to the serial ALU of adjacent video processors;

control inputs in common with all of said video processors receiving control and address sets of bits to select operation of the multiplexer means and addressing of said first and second random-access memories to thereby perform one-bit serial arithmetic/logic operations in each of the video processors for each set of control and address bits;

address means addressing the input registers of said plurality of serial video processors in a repeating sequence correlated with a raster scan to load said multi-bit video data from said input into said input registers;

said address means also addressing the output registers of said plurality of serial video processors in a repeating sequence correlated with a raster scan to transfer processed multi-bit video data to an output;

control means having a multi-bit parallel output connected in common to said control inputs of all of said serial video processors to apply sequences of sets of control and address bits to said control inputs to result in real-time processing of said multi-bit video data.

2. A system according to claim 1 wherein an analog system input is connected to said input through an analog-to-digital converter, and said output is connected to an analog system output through a digital-to-analog converter.

3. A system according to claim 2 wherein said analog system input is sampled at a rate which is related to a multiple of the horizontal scan rate of said raster scan, said multiple being at least equal to the number of serial video processors.

4. A system according to claim 3 wherein there are at least as many of said serial video processors as there are pixels in a horizontal scan of said raster scan.

5. A system according to claim 1 wherein said first and second memories comprise a dynamic random access memory having one differential sense amplifier for each of the serial video processors.

6. A system according to claim 1 wherein said input register of each video processor includes a first set of bits connected to receive said multi-bit video data from said input and a second set of bits connected to outputs of a frame memory.

7. A system according to claim 6 wherein said output register of each video processor includes a first set of bits connected to transfer said multi-bit processed data from said video processor to said output and a second set of bits connected to transfer processed data to inputs of said frame memory.

8. A system according to claim 7 wherein there are at least as many of said serial video processors as the number of pixels in a horizontal scan of said raster scan, and there is a delay of at least one of said horizontal scans between input of video data to said input and output of processed data at said output.

9. A system according to claim 8 wherein said frame memory stores processed video data for one frame of said raster scan.

10. A system according to claim 1 wherein each of said first and second random-access memories has a number of bits many times the number of bits in said input and output registers.

11. A serial processor system for high-speed processing comprising:

an input for receiving digitized, multi-bit signal data;

a plurality of serial processors in a linear array, each serial processor having;

an input register connected to receive said multi-bit signal data from said input;

an output register connected to transfer multi-bit processed data from the serial processor;

random-access memory means having data inputs and outputs connected to said input and output registers and having at least one address input;

a serial ALU element having a plurality of one-bit registers and multiplexer means to connect inputs and outputs of each said registers to data inputs and outputs of said random-access memory means, the multiplexer means also capable of connecting inputs and outputs of some of the one-bit registers to the serial ALU element of adjacent serial processors;

control inputs in common with all of said serial processors receiving sets of control and address bits to select operation of the multiplexer means and addressing of said random-access memory means to thereby perform one-bit serial arithmetic/logic operations in each of the serial processors for each set of control and address bits;

first address means addressing the input registers of said plurality of serial processors in a repeating sequence correlated with said signal data to load said multi-bit signal data from said input into said input registers; and

second address means addressing the output registers of said plurality of serial processors in a repeating sequence to transfer processed multi-bit data to an output;

control means having a multi-bit parallel output connected in common to said control inputs and address inputs for all of said serial processors to apply sequences of sets of control and address bits to said control inputs to result in high-speed processing of said multi-bit signal data.

12. A system according to claim 11 wherein said random-access memory means includes first and second memories comprising dynamic random-access memory having one differential sense amplifier for each of the first and second memories for each of the serial processors.

13. A system according to claim 11 wherein said input register of each serial processor includes a first set of bits connected to receive said multi-bit signal data from said input and a second set of bits connected to outputs of an auxiliary memory.

14. A system according to claim 11 wherein said random-access memory means has a number of bits many times the number of bits in said input and output registers.

15. A method of real-time processing of a raster-scanned video signal, comprising the steps of:

converting the video signal to multi-bit digital data at a sampling rate, and storing said digital data in a set of input registers, there being a number of said input registers corresponding to the number of pixels in a horizontal scan of the raster scan,

transferring the digital data in said registers to memory cells of a set of data memories,

performing a plurality of serial arithmetic/logic operations on said digital data in said set of data memories and returning processed data to said data memories in a set of one-bit serial processor elements, there being a corresponding one processor element for each of said input registers,

transferring the processed digital data from said set of data memories to a set of output registers, there being a number of said output registers corresponding to said number of input registers,

and converting digital data in said output registers to an output video signal.

16. A method according to claim 15 including the steps of storing processed video data from said set of output registers in a frame memory containing a set of memory cells for each pixel of all of said horizontal scans in one vertical scan of the raster scan, and transferring the stored video data to said set of input registers in synchronization with the converting of the video signal, whereby the input registers contain data from the stored frame and also converted data for the current horizontal scan.

17. A method according to claim 15 wherein, said step of performing serial arithmetic/logic operations is performed simultaneously in all of said processor elements.

18. A method according to claim 15 wherein at least two of said horizontal scans occurs between said step of storing the digital data in the one of the set of input registers and said step of transferring digital data from the set of data memories to said output register for a given pixel of one of said horizontal scans.

19. A method according to claim 15 wherein said set of data memories consists of first and second dynamic one-bit wide random-access memories having sense amplifiers clocked in synchronization with clocking of said serial processor elements.

20. A method of high-speed signal processing, comprising the steps of:

converting an input signal to multi-bit digital data at a sampling rate, and loading in parallel said digital data in a set of input registers,

transferring the digital data from said register to memory cells of a set of one-bit wide data memories, the data memories having a number of bits greatly exceeding the number of bits in one of said input registers,

performing a plurality of serial arithmetic/logic operations on said digital data in said set of data memories and returning processed data to said data memories in a set of one-bit serial processor elements, there being a corresponding one processor element for each of said input registers,

transferring one bit at a time the processed digital data from said set of data memories to a set of output registers, there being a number of said output registers corresponding to said number of input registers.

21. A method according to claim 20 including the steps of storing processed data from said set of output registers in a buffer memory for a period of time during which said input signal makes a complete cycle of a repeating sequence, and transferring the stored processed data to said set of input registers in synchronization with the converting of the input signal, whereby the input registers contain data from the buffer memory and also converted data for the current input signal.

22. A method according to claim 20 wherein said step of performing serial arithmetic/logic operations is performed simultaneously in all of said processor elements.

23. A method according to claim 20 wherein said set of data memories includes first and second dynamic random-access memories having sense amplifiers clocked in synchronization with clocking of said serial processor elements.

24. A video system comprising:

a video display;

a video signal receiver for receiving signal data;

a controller operative to supply control signals; and

a plurality of processors coupled such that said data is sequentially received and stored in a linear array across said plurality of processors, each processor having;

a first register operative to receive a part of said signal data from said video signal receiver in parallel;

a second register coupled to said video display;

a memory circuit having portions respectively connected to said first and said second registers for transferring data to and from the first and second registers serially; and

an arithmetic logic unit, connected to said memory circuit and said controller, responsive to the control signals from said controller for performing an arithmetic operation of the data received from said memory circuit.

25. The video system of claim 24 wherein said memory circuit comprises a first memory unit connected to said first register and a second memory unit connected to said second register.

26. The video system of claim 24 further comprising a decoder, connected to said controller and to said processors, said decoder responsive to control signals for generating an address signal to access the data locations of said memory circuit.

27. The video system of claim 24 further comprising an input means for selectively directing data inputs from said video signal receiver to said first register of the respective processor.

28. The video system of claim 24 further comprising an output means for selectively directing data outputs from said second register of the respective processor to said video display.

29. An image processing system comprising:

an image input receiver for receiving serial image data;

an analog-to-digital (A/D) converter connected to said image input receiver;

a controlling circuit;

a plurality of processors coupled such that said data is received sequentially and stored in a linear array across said plurality of processors and connected to said controlling circuit each said processor having;

an input register operative to receive digital image data in parallel;

a storage circuit including first and second portions, and first portion connected to said input register so as to receive data serially;

an output register connected to said second portion so as to receive data serially and operative to hold output data; and

a computing circuit connected to said storage circuit operative to perform an arithmetic operation on data received from said storage circuit;

a digital-to-analog (D/A) converter connected to said output register; and

an image output device connected to said D/A converter operative to receive signals from said D/A converter.

30. The image processing system of claim 29 further comprising a first and a second computing register, connected to said computing circuit and said storage circuit, wherein said computing circuit is responsive to control signals from said controlling circuit to perform an arithmetic operation on data from said registers and store computed data in one of said registers.

31. The image processing system of claim 29 wherein said controlling circuit also controls data transfers between said processors.

32. The image processing system of claim 29 further comprising a first and a second computing register, connected to said computing circuit and said storage circuit, wherein said storage circuit comprises a first storage device connected between said input register and said first computing register and a second storage device connected between said output register and said second computing register.

33. The image processing system of claim 29 further comprising a commutator circuit, connected to said controlling circuit and said processors, for controlling data flow to and from said D/A and said A/D converter.

34. The image processing system of claim 29 further comprising a frame memory, connected to said controlling circuit and said processors, having a plurality of data storage locations.

35. The image processing system of claim 34 further comprising a commutator circuit, connected to said controlling circuit, said processors and said frame memory, operative to control data flow between said processors and said frame memory.

36. An image data processing device comprising:

a plurality of computing circuits coupled such that said data is sequentially receive and stored in a linear array across said plurality of computing circuits, each computing circuit having;

an input register connected to receive signal in parallel data;

an output register;

a memory circuit including portions connected to said input and said output register for transferring data to and from the input and output registers serially;

an arithmetic circuit connected to said memory circuit operative to perform an arithmetic operation on data received; and

a controller circuit connected to said computing circuits for controlling the operation of said computing circuits.

37. The image data processing device of claim 36 further comprising an input computing register and an output computing register, connected to said controller circuit and said memory circuit, wherein said arithmetic circuit is responsive to a control signal from said controller circuit to perform an arithmetic operation on data from said registers and to store resulting data in one of said registers.

38. The image data processing device of claim 36 wherein said memory circuit comprises an input memory circuit and an output memory circuit connected to said input computing register and said output computing register respectively.

39. The image data processing device of claim 38 further comprising an input decoder and an output decoder, connected to said input memory circuit and said output memory circuit respectively and to said controller circuit, and responsive to a coded signal from said controller to decode the coded signal for addressing the memory locations of said memory circuits.

40. The image data processing device of claim 39 wherein said input decoder and said output decoder are also connected to said input register and said output register respectively, and are responsive to a coded signal from said controller circuit to decode the coded signal for controlling data transfers of said input register and said output register.

41. The image data processing device of claim 36 further comprising a commutator circuit, connected to said controller circuit and said computing circuits, and responsive to a control signal from said controller.

42. The image data processing device of claim 36 further comprising a frame memory, connected to said controller circuit and said computing circuits.