Digital image processor

• US 5,321,772 A
• Filed: 01/24/1991
• Issued: 06/14/1994
• Est. Priority Date: 03/05/1990
• Status: Expired due to Fees

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Sawyer, Darrell D.
• Primary Examiner(s): Razavi, Michael
• Application Number:
  US07/645,210
• Time in Patent Office: 1,237 Days
• Field of Search: 382/10, 382/30, 382/33, 382/34
• US Class Current: 382/216
• CPC Class Codes: G06V 10/751 Comparing pixel values or logical combinations thereof, or feature values having positional relevance, e.g. template matching

Abstract

A digital image processor is described in which the output from a linear array of electro-optic sensors, first having been signal conditioned and digitized, is then loaded into a RAM image memory forming a part of the microprocessor-based template matching processor. The image memory functions like a shift device and as the sensor image signals are shifted therethrough, they are compared on a bit-by-bit basis with digital signals stored in a PROM which comprise a plurality of templates with which the scanned image is to be compared. The extent of correspondence between the image being sensed and the templates is then accumulated and if the sum exceeds a predetermined threshold, a match between the image being sensed and the template is established. The system is implemented using gate array technology such that the common template concept is feasible in those applications requiring very small size and low power dissipation.

Claims

1. Image processing apparatus comprising, in combination:

(a) electro-optic linear scanning means for simultaneously scanning an object along multiple lines comprising a field-of-view and simultaneously producing a plurality of analog electrical output signals characteristic of said object as observed along said multiple lines, each one of said output signals corresponding to a respective line;

(b) signal conditioning means coupled to said linear scanning means for simultaneously converting said plurality of analog electrical output signals to a corresponding plurality of digital signal trains;

(c) template matching processor means including image memory means having parallel data input means, parallel data output means, said image memory means being paritioned into a plurality of N-bit registers each coupled to a respective one of said digital signal trains, and template storage means for storing a plurality of digital signal patterns together defining the ideal two-dimensional shape characteristics of said object, said template storage means including parallel data output means;

(d) controller means coupled to said linear scanning means and said signal conditioning means for selectively establishing the amplitude threshold and sampling frequency for said analog output signals in forming said digital signal trains, said controller means controlling the entry of each said plurality of digital signal trains into said respective plurality of N-bit registers of said image memory means in said template matching processor means for an instantaneous field-of-view;

(e) said template matching processor means further including control means coupled to receive sample clock signals from said signal conditioning means for producing timing signals for said image memory means and said template storage means;

(f) comparator means coupled to said parallel data output means of said image memory means and said template storage means for performing a bit-by-bit logical AND comparison of each of said digital signal trains with a respective one of said digital signal patterns stepped out of the respective N-bit registers of said image memory means and template storage means by said timing signals; and

(g) means for summing the result of said logical AND comparison to generate a degree of correlation signal.

3. The image processing apparatus as in claim 1 wherein said controller means is operatively coupled to more than one of said linear scanning means, signal conditioning means and template matching processor means.

4. The image processing apparatus as in claim 1 wherein said image memory means comprises a plurality of N-bit shift registers coupled to the output of said signal conditioning means, each of said shift registers including said parallel data output means which are individually coupled to tri-state buffering means, and decoder means coupled to receive a row count value from said signal conditioning means, said decoder means having plural output lines individually coupled to said tri-state buffering means for sequentially gating N-bit words from said shift registers to said comparator means.

5. The image processing apparatus as in claim 1 wherein said comparator means comprises a plurality of AND logic circuits, each having first and second inputs for receiving a first N-bit word from said image memory means on said first inputs and a corresponding N-bit word from said template storage means on said second inputs, said AND logic circuits providing address inputs;

and ROM encoding means coupled to receive said address inputs from said AND logic circuit means and storing count values at addressable locations therein corresponding to the number of signals in said address inputs of a given binary significance.

6. The image processing apparatus as in claim 5 wherein said means for tallying comprises digital adding means coupled to receive said count values from said ROM encoding means for developing a total of the number of signals of a given binary significance read out from said ROM encoding means.

7. The image processing apparatus as in claim 6 and further including further comparator means for comparing said total of the number of signals of a given binary significance to a predetermined threshold count.

2. Image processing apparatus comprising:

(a) a plurality of electro-optical sensing elements arranged in a linear array;

(b) scanning means for focusing electro-magnetic radiation from an object to be identified onto said linear array for simultaneously producing a plurality of analog signals arranged in n-row by m-columns as said scanning means effectively sweeps said object at selectable intervals;

(c) signal conditioning means connected to said sensing elements for simultaneously converting each one of said analog signals into a corresponding M-digital word of N-bits, the number of said M-digital words corresponding to said m-columns being sequentially generated;

(d) controller means operatively coupled to said scanning means and said signal conditioning means for sequencing the formation of said plurality of groups of M-digital words of N-bits each and producing sample clock signals for said image memory means;

(e) template matching processor means including image memory means having a plurality of N-bit shift registers each coupled to said signal conditioning means for sequentially receiving respective N-bit words in parallel format, said template matching processor means further including a ROM memory means storing a plurality of N-bit words characterizing a plurality of templates of M-columns each and control means receiving sample clock signals from said signal conditioning means for producing timing signals for said image memory means and said ROM memory means whereby sais M-digital workds of N-bits each are simultaneously stepped out in parallel from said image memory means and said ROM memory means; and

(f) means for accumulating a tally of the number of matches between the binary signaificance of bits comprising the N-bit words being simultaneously stepped from said image memory means and said ROM memory means.

8. The image processing apparatus as in claim 2 wherein said means for accumulating a tally comprises:

(a) N two-input AND gates coupled to the data outputs of said image memory means and said ROM memory for comparing the binary significance of each bit of each word read from said image memory means with the corresponding bits read out from said ROM memory means;

(d) encoding means coupled to the output of said N two-input AND gates for producing a count value corresponding to the number of matches determined by said AND gates for successive N-bit words; and

(c) adding means for summing said count values for M successive N-bit words applied to said N two-input AND gates.