Method and apparatus for transmitting graphics command in a computer graphics system

• US 5,321,806 A
• Filed: 08/21/1991
• Issued: 06/14/1994
• Est. Priority Date: 08/21/1991
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Krishnaswami, Srinivasan, Masucci, Agnes, Moezzi, Ali, Case, Colyn, Meinerth, Kim, Irwin, John
• Primary Examiner(s): Shaw, Dale M.
• Assistant Examiner(s): Tung, Kee M.
• Application Number:
  US07/748,360
• Time in Patent Office: 1,028 Days
• Field of Search: 395/162, 395/164, 395/166, 395/375, 340/799, 340/798
• US Class Current: 345/522
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/127 Updating a frame memory using a transfer of data from a source area to a destination area
• CPC Class Codes: G09G 5/06 using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/08 Cursor circuits
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

A residue buffer, for temporary storage of portions of transmissions from a CPU to a graphics processor. Graphics commands are transmitted, in transmission units of uniform size, from a processor unit to an address generator, which processes the commands. The portion of the transmission unit not immediately usable by the graphics processor is stored in the residue buffer. The disclosure further describes a computer graphics system, having a graphics processor capable of reading from or writing to main memory, including virtual memory, without any action by the CPU; having a duplicate cache tag store accessible by the graphics system without generating traffic on the system bus; having a FIFO command buffer in main memory for temporary storage of graphics commands; having a "short circuit" feature for routing graphics commands to the command processor in the minimum number of steps; having a cursor control system capable of storing cursor pattern information in, and retrieving cursor pattern information from, main memory; having a cursor bus that is reconfigurable to carry information other than cursor information; and having a frame buffer module that contains no timing or cursor control circuitry.

Claims

1. A computer graphics system, comprising

a CPU for generating graphics commands of variable length, each of said graphics commands having a first indicator for marking a beginning of said graphics command and a second indicator for denoting the length of said graphics command;

a graphics processor for processing said graphics commands;

means for transmitting a transmission unit having a predetermined fixed length from said CPU to the graphics processor, said transmission unit containing at least a portion of one of said graphics commands;

means for storing said portion of a graphics command;

means, associated with said graphics processor for receiving said transmission unit and for determining if said transmission unit contains a complete graphics command;

means, responsive to said receiving and determining means, for routing said complete graphics command to said graphics processor; and

means for combining portions of subsequently transmitted transmission units with said stored portion of said transmission unit to form a complete graphics command.

2. The computer system as claimed in claim 1 wherein

said transmission unit contains a plurality of graphics commands,

said receiving and determining means detects said first indicator and said second indicator of a first one of said plurality of graphics commands to determine the part of said transmission unit containing said first one graphics command;

said routing means routes said first one graphics command to said graphics processor; and

said directing means directs the others of said plurality of graphics commands to said storing means.

3. The computer system as claimed in claim 2, further comprising

means, for monitoring said graphics processor for its availability to process a graphics command;

and

means, responsive to said monitoring means, for sending another of said plurality of graphics commands to the graphics processor.

4. The computer system as claimed in claim 3, wherein said transmitting means comprises

a second of a main memory for storing said graphics commands;

and

means for assembling said graphics commands from said section of main memory into said transmission units.

5. The computer system as claimed in claim 4, further comprising a frame buffer memory, connected to said bus, for storing data for display on a video device, wherein the processing of the graphics commands by the graphics processor overwrites said data stored in said frame buffer memory.

6. The computer graphics system as claimed in claim 1 further comprising

first determining means for determining if said graphics processor is available to process a graphics command;

second determining means for determining if said storage means contains a complete graphics command; and

means, responsive to said first and second determining means for sending said complete graphics command to said graphics processor.

7. The computer system as claimed in claim 1 wherein said transmitting means comprises

a section of main memory, for storing said graphics commands;

and

means for assembling said graphics commands from said section of main memory, into said transmission units.

8. The computer system as claimed in claim 1 further comprising a frame buffer memory connected to said bus for storing data for display on a video device, wherein the processing of the graphics commands by the graphics processor overwrites said data stored in said frame buffer memory.

9. A computer graphics system, comprising:

a CPU for issuing graphics commands to a graphics processor, the graphics commands having a variable length, each graphics command having a first indicator for marking a beginning of said graphics command and a second indicator for denoting the length of said graphics command;

means for transmitting said graphics commands from said CPU to a main memory, said main memory having a portion for temporarily storing graphics commands issued by said CPU;

means for transmitting said graphics commands from said main memory to said graphics processor in transmission units, said transmission units having a fixed predetermined length and containing a first graphics command and a portion of a second graphics command;

means for separating the first graphics command from said portion of a second graphics command;

means for routing the separated first graphics command to said graphics processor;

means for storing said portion of said second graphics command; and

means for combining subsequently transmitted portions of graphics commands with said stored portion of said second graphics command to form a complete graphics command.

10. The computer graphic system as claimed in claim 9 wherein said transmission unit contains a plurality of graphics commands, and wherein

said separating means separates the first of the plurality of graphics commands from the remainder of the plurality of graphics commands;

said routing means routes the first of the plurality of graphics commands to said graphics processor; and

said storing means stores the remainder of said plurality of graphics commands.