Layout scheme for precise capacitance ratios

• US 5,322,438 A
• Filed: 06/18/1993
• Issued: 06/21/1994
• Est. Priority Date: 06/18/1993
• Status: Expired due to Term

• Current Assignee: Silicon Systems, Inc. (Texas Instruments, Inc.)
• Original Assignee: Silicon Systems, Inc. (Texas Instruments, Inc.)
• Inventors: McNutt, Michael, Hershbarger, Russell
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US08/079,646
• Time in Patent Office: 368 Days
• Field of Search: 437/51, 437/60, 437/919
• US Class Current: 716/115
• CPC Class Codes: H01L 27/0805 Capacitors only

Abstract

The present invention relates to the field of capacitor layout schemes for integrated circuits. A method comprising nine specific layout criteria is disclosed that eliminates or greatly suppresses problems of prior art capacitance matching. The nine layout criteria for providing precise capacitance ratios are: 1) fixed horizontal and vertical spacings are maintained for unit capacitors; 2) grounded dummy unit capacitors are placed around the periphery of each capacitor group; 3) two interconnects are used per unit capacitor; 4) equal numbers of top and bottom external interconnects per capacitance are maintained; 5) the external interconnect capacitance is made equal to the internal interconnect capacitance; 6) nonunit capacitors are used in the largest capacitance in a ratio; 7) the top plate interconnect of a capacitance is isolated from the bottom plate interconnect of the same capacitance; 8) interconnects are shielded from opposite capacitor plates; and, 9) rows of unit capacitors of the same capacitance are isolated from each other. This layout scheme provides improved accuracy and reproducibility for capacitance matching in silicon integrated circuits. Another advantage of this method is that, by limiting the options available for laying out matched capacitor structures, the layout process is streamlined in a manner that reduces time and, in particular, lends itself to automation. Still another advantage of it is that less space is required for the same circuit in most cases.

Claims

1. A method for precise capacitance ratios comprising the steps of:

maintaining fixed horizontal and vertical spacings for N unit capacitors, said N unit capacitors forming M groupings of unit capacitors wherein M≦

N, said M groupings of unit capacitors forming a plurality of capacitances;

placing a plurality of grounded dummy capacitors around a periphery of each of said M groupings of unit capacitors;

using two interconnect means per unit capacitor for coupling a unit capacitor to external circuitry and to unit capacitors of one of said M groupings of unit capacitors;

maintaining equal numbers of top and bottom external interconnect means per capacitance of said plurality of capacitances;

making a capacitance of said external interconnect means equal to a capacitance of said internal interconnect means;

using one or more nonunit capacitors in a largest capacitance of said plurality of capacitances in a ratio;

isolating a top plate interconnect means of each of said plurality of capacitances from a bottom plate interconnect means of each of said same capacitances;

shielding said interconnect means from the opposite capacitor plates; and

isolating a plurality of rows of unit capacitors, said plurality of rows of unit capacitors forming a capacitance of said plurality of capacitances.

2. The method of claim 1 wherein said step of maintaining said fixed horizontal and vertical spacings for said N unit capacitors comprises the steps of:

maintaining a fixed channel width for said interconnect means; and

,

spacing said N unit capacitors equidistantly for equalizing fringe capacitances.

3. The method of claim 1 wherein said step of making a capacitance of said external interconnect means equal to a capacitance of said internal interconnect means comprises the steps of:

establishing POLY1-POLY2 underlap at minimum design criterion;

calculating said capacitance of an external interconnect means to a POLY1 layer;

calculating said capacitance/length of internal interconnect means to said POLY1 layer; and

,

choosing a space between said unit capacitors for equalizing said capacitances of said internal and external interconnect means.

4. The method of claim 1 wherein said step of using two interconnect means per unit capacitor comprises the steps of:

using two interconnect means for a unit capacitor or a nonunit capacitor having an area that is greater than or equal to 1.0 and less than or equal to 1.24;

using three interconnect means for a nonunit capacitor having an area that is greater than or equal to 1.25 and less than or equal to 1.74; and

,

using four interconnect means for a nonunit capacitor having an area that is greater than of equal to 1.75.

5. A method using a double metal process for precise capacitance ratios comprising the steps of:

maintaining fixed horizontal and vertical spacings for N unit capacitors, said N unit capacitors forming M groupings of unit capacitors wherein M≦

N, said M groupings of unit capacitors forming a plurality of capacitances;

placing a plurality of grounded dummy capacitors around a periphery of each of said M groupings of unit capacitors;

using two interconnect means per unit capacitor for coupling a unit capacitor to external circuitry and to unit capacitors of one of said M groupings of unit capacitors;

using one or more nonunit capacitors in a largest capacitance of said plurality of capacitances in a ratio; and

,

isolating a top plate interconnect means of each of said plurality of capacitances from a bottom plate interconnect means of each of said same capacitances.

6. The method of claim 5 wherein said step of maintaining said fixed horizontal and vertical spacings for said N unit capacitors comprises the steps of:

maintaining a fixed channel width for said interconnect means; and

,

spacing said N unit capacitors equidistantly for equalizing fringe capacitances.