Silicon carbide field effect device

• US 5,323,040 A
• Filed: 09/27/1993
• Issued: 06/21/1994
• Est. Priority Date: 09/27/1993
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures Holding 78 LLC (Intellectual Ventures LLC)
• Original Assignee: North Carolina State University At Raleigh
• Inventors: Baliga, Bantval J.
• Primary Examiner(s): NGO, NGAN V
• Application Number:
  US08/127,309
• Time in Patent Office: 267 Days
• Field of Search: 257/77, 257/329, 257/330, 257/331, 257/332, 257/334, 257/344
• US Class Current: 257/332
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A silicon carbide field effect device includes vertically stacked silicon carbide regions of first conductivity type, extending from a lowermost drain region to an uppermost source region. In between the drain and source regions, a drift region and a channel region are provided. The drift region extends adjacent the drain region and the channel region extends between the drift region and the source region. Control of majority carrier conduction between the source and drain regions is provided by a plurality of trenches, which extend through the source and channel region, and conductive gate electrodes therein. To provide high blocking voltage capability and low on-state resistance, the doping concentration in the drift region is selected to be greater than the doping concentration of the channel region but below the doping concentration of the drain and source regions. Preferably, the material used for the gate electrodes, the spacing between adjacent trenches and the doping concentration of the channel region are chosen so that the channel region is depleted of majority charge carriers when zero potential bias is applied to the gate electrodes.

Claims

1. A silicon carbide field effect transistor comprising:

a silicon carbide substrate having first and second opposing faces;

a silicon carbide drain region of first conductivity type in said silicon carbide substrate, extending to said first face;

a silicon carbide drift region of first conductivity type on said silicon carbide drain region opposite said first face, said silicon carbide drift region having a first conductivity type dopant concentration below that of said silicon carbide drain region;

a silicon carbide channel region of first conductivity type on said silicon carbide drift region opposite said silicon carbide drain region, said silicon carbide channel region having a first conductivity type dopant concentration below that of said silicon carbide drift region;

a silicon carbide source region of first conductivity type on said silicon carbide channel region, said silicon carbide source region extending to said second face and having a first conductivity type dopant concentration above that of said silicon carbide channel region;

a first trench in said silicon carbide substrate at said second face, said first trench having a sidewall extending between said silicon carbide drift region and said silicon carbide source region; and

a second trench in said silicon carbide substrate at said second face, adjacent said first trench, said second trench having a sidewall extending between said silicon carbide drift region and said silicon carbide source region to thereby define a mesa of first conductivity type in said silicon carbide channel region and said silicon carbide source region, between said first trench and said second trench.

2. The silicon carbide field effect transistor of claim 1, further comprising a first insulating region on said first trench sidewall and a second insulating region on said second trench sidewall.

3. The silicon carbide field effect transistor of claim 2, further comprising a first conductive gate electrode in said first trench on said first insulating region and a second conductive gate electrode in said second trench on said second insulating region.

4. The silicon carbide field effect transistor of claim 3, wherein said first trench has a bottom adjacent said silicon carbide drift region and said second trench has a bottom adjacent said silicon carbide drift region, and wherein said first insulating region extends along said first trench bottom and said second insulating region extends along said second trench bottom.

5. The silicon carbide field effect transistor of claim 3, wherein said first conductive gate electrode has a first work function potential, and said second conductive gate electrode has a second work function potential and said silicon carbide channel region has a third work function potential, and wherein said first, second and third work function potentials are selected to deplete mobile charge carriers of first conductivity type from said silicon carbide channel region.

6. The silicon carbide field effect transistor of claim 5, wherein said first, second and third work function potentials are selected to fully deplete mobile charge carriers of first conductivity type from said silicon carbide channel region.

7. The silicon carbide field effect transistor of claim 5, wherein said first, second and third work function potentials are selected to fully deplete mobile charge carriers of first conductivity type from said mesa when said first conductive gate electrode and said second conductive gate electrode are both at zero potential bias, with respect to said silicon carbide drain region.

8. The silicon carbide field effect transistor of claim 4, wherein said silicon carbide channel region comprises monocrystalline silicon carbide and wherein said first trench and said second trench are formed by simultaneously amorphizing adjacent portions of said monocrystalline silicon carbide channel region to define adjacent amorphous silicon carbide regions and then removing the amorphous silicon carbide regions.

9. A silicon carbide field effect transistor comprising:

a silicon carbide substrate having first and second opposing faces;

a silicon carbide drain region of first conductivity type in said silicon carbide substrate, extending to said first face;

a silicon carbide drift region of first conductivity type on said silicon carbide drain region opposite said first face, said silicon carbide drift region having a first conductivity type dopant concentration below that of said silicon carbide drain region;

a silicon carbide channel region of predetermined conductivity type on said silicon carbide drift region opposite said silicon carbide drain region, said silicon carbide channel region having a first conductivity type dopant concentration below that of said silicon carbide drift region;

a silicon carbide source region of first conductivity type on said silicon carbide channel region, said silicon carbide source region extending to said second face and having a first conductivity type dopant concentration above that of said silicon carbide channel region; and

at least one trench in said silicon carbide substrate at said second face, said trench extending between said second face and said silicon carbide drift region and having a sidewall which defines a mesa, extending between said silicon carbide drift region and said second face.

10. The silicon carbide field effect transistor of claim 9, further comprising an insulating region on said trench sidewall.

11. The silicon carbide field effect transistor of claim 10, further comprising a conductive gate electrode in said trench, extending along said insulating region.

12. The silicon carbide field effect transistor of claim 11, wherein said conductive gate electrode has a first work function potential and said silicon carbide channel region has a second work function potential, and wherein a difference between said first work function potential and said second work function potential is preselected to deplete mobile charge carriers of first conductivity type from said silicon carbide channel region.

13. The silicon carbide field effect transistor of claim 12, wherein said difference is preselected to fully deplete mobile charge carriers of first conductivity type from said silicon carbide channel region when said conductive gate electrode is at zero potential bias, with respect to said silicon carbide drain region.

14. The silicon carbide field effect transistor of claim 11, wherein said silicon carbide channel region comprises monocrystalline silicon carbide and wherein said trench is formed by amorphizing a portion of said silicon carbide substrate to define an amorphous silicon carbide region and then removing the amorphous silicon carbide region to define said mesa.

15. A silicon carbide field effect transistor comprising:

a silicon carbide substrate having first and second opposing faces;

a silicon carbide drain region of first conductivity type in said silicon carbide substrate, extending to said first face;

a silicon carbide drift region of first conductivity type on said silicon carbide drain region opposite said first face, said silicon carbide drift region having a first conductivity type dopant concentration below that of said silicon carbide drain region;

a silicon carbide channel region of first conductivity type on said silicon carbide drift region opposite said silicon carbide drain region, said silicon carbide channel region extending to said second face and having a first conductivity type dopant concentration below that of said silicon carbide drift region;

a first trench in said silicon carbide substrate at said second face, said first trench having a first sidewall extending between said silicon carbide drift region and said second face; and

a second trench in said silicon carbide substrate at said second face, adjacent said first trench, said second trench having a second sidewall, opposite said first trench sidewall, extending between said silicon carbide drift region and said second face.

16. The silicon carbide field effect transistor of claim 15, further comprising a first insulating region on said first trench sidewall and a second insulating region on said second trench sidewall.

17. The silicon carbide field effect transistor of claim 16, further comprising a first conductive gate electrode in said first trench on said first insulating region and a second conductive gate electrode in said second trench on said second insulating region.

18. The silicon carbide field effect transistor of claim 17, wherein said first conductive gate electrode has a first work function potential, and said second conductive gate electrode has a second work function potential and said silicon carbide channel region has a third work function potential, and wherein said first, second and third work function potentials are selected to deplete mobile charge carriers of first conductivity type from said silicon carbide channel region.

19. The silicon carbide field effect transistor of claim 18, wherein said first, second and third work function potentials are selected to fully deplete mobile charge carriers of first conductivity type from said silicon carbide channel region when said first conductive gate electrode and said second conductive gate electrode are both at zero potential bias, with respect to said silicon carbide drain region.

20. The silicon carbide field effect transistor of claim 18, further comprising a silicon carbide source region of first conductivity type on said second face, electrically contacting said silicon carbide channel region, said silicon carbide source region having a first conductivity type dopant concentration above that of said silicon carbide channel region.

21. The silicon carbide field effect transistor of claim 20, further comprising a drain contact on said silicon carbide drain region, opposite said first face, and a source contact on said silicon carbide source region, opposite said second face.

22. A silicon carbide rectifier, comprising:

a monocrystalline silicon carbide substrate having first and second opposing faces;

a silicon carbide drain region of first conductivity type in said silicon carbide substrate, extending to said first face;

a silicon carbide drift region of first conductivity type on said silicon carbide drain region opposite said first face, said silicon carbide drift region having a first conductivity type dopant concentration below that of said silicon carbide drain region;

a silicon carbide channel region of first conductivity type on said silicon carbide drift region opposite said silicon carbide drain region, said silicon carbide channel region having a first conductivity type dopant concentration below that of said silicon carbide drift region;

a silicon carbide source region of first conductivity type on said silicon carbide channel region, said silicon carbide source region extending to said second face and having a first conductivity type dopant concentration above that of said silicon carbide channel region;

a first trench in said silicon carbide substrate at said second face, said first trench having a sidewall extending between said silicon carbide drift region and said silicon carbide source region;

a second trench in said silicon carbide substrate at said second face, adjacent said first trench, said second trench having a sidewall extending between said silicon carbide drift region and said silicon carbide source region to thereby define a mesa of first conductivity type in said silicon carbide channel region and said silicon carbide source region, between said first trench and said second trench;

a first insulating region on said first trench sidewall and a second insulating region on said second trench sidewall;

a first conductive gate electrode in said first trench on said first insulating region and a second conductive gate electrode in said second trench on said second insulating region;

a drain contact on said silicon carbide drain region, at said first face; and

a source contact on said silicon carbide source region, at said second face, said source contact electrically connected to said first conductive gate electrode and said second conductive gate electrode.

23. The silicon carbide rectifier of claim 22, wherein said first conductive gate electrode has a first work function potential, and said second conductive gate electrode has a second work function potential and said silicon carbide channel region has a third work function potential, and wherein said first, second and third work function potentials are selected to fully deplete mobile charge carriers of first conductivity type from said silicon carbide channel region, when said source contact is at zero potential bias, with respect to said drain contact.

24. The silicon carbide rectifier of claim 23, wherein said first trench and said second trench are formed by simultaneously amorphizing adjacent portions of said monocrystalline silicon carbide channel region to define adjacent amorphous silicon carbide regions and then removing the amorphous silicon carbide regions to define said mesa.