Low power low temperature ECL output driver circuit

• US 5,323,068 A
• Filed: 11/17/1992
• Issued: 06/21/1994
• Est. Priority Date: 11/17/1992
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Freitas, Oscar W.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): DRISCOLL, BENJAMIN
• Application Number:
  US07/977,812
• Time in Patent Office: 581 Days
• Field of Search: 307/455, 307/443, 307/475, 307/494, 307/310
• US Class Current: 326/126
• CPC Class Codes: H03K 19/00376 in bipolar transistor circuits
• CPC Class Codes: H03K 19/086 Emitter coupled logic

Abstract

A temperature compensated ECL output driver circuit incorporates an ECL output gate (Q4,Q3) coupled between high (V_CC) and low (V_EE) potential power rails with output voltage swing resistors (R2, R1). The ECL output gate provides an output node (N1) at the collector node of one of the ECL output gate transistors (Q4). A first current sink (Q5,R4) is coupled between the common emitter node coupling (N3) of the ECL output gate (Q4,Q3) and low potential power rail (V_EE). A compensating current source (Q11,R5) is coupled to the ECL output gate output node (N1) for generating a supplementary compensating current during operation of the ECL output driver circuit in intermediate and high temperature operating ranges. A compensating current switch (Q9,Q10) is coupled in the compensating current path and is constructed for switching off the supplementary compensating current in a specified low temperature operating range to maintain the logic high output signal V_OH within specifications. The compensating current switch is an ECL compensating current switch (CCS) gate (Q9,Q10) and the compensating current source is a second current sink (Q11,R5) coupled to the ECL CCS gate.

Claims

1. A temperature compensated ECL output driver circuit comprising an ECL output gate coupled between high and low potential power rails and having first and second ECL output gate transistors with a first common emitter node coupling providing alternative collector current paths through respective output voltage swing resistors according to data input signals at a base node input of one of the ECL output gate transistors, said ECL output gate providing an output node at the collector node of one of the ECL output gate transistors, and a first current sink coupled between the first common emitter node coupling and low potential power rail, the improvement for operation of the ECL output driver circuit at low power and low temperature comprising:

a compensating current source coupled to the ECL output gate output node for generating a supplementary compensating current during operation of the ECL output driver circuit in intermediate and high temperature operating ranges in a compensating current path through the output voltage swing resistor coupled to said output node to permit operation of the first current sink of the ECL output gate at relatively low power;

and an ECL compensating current switch (CCS) gate coupled in the compensating current path and constructed for switching off the supplementary compensating current in a specified low temperature operating range.

2. The ECL output driver circuit of claim 1 wherein the compensating current source is a second current sink coupled between the ECL CCS gate and low potential power rail.

3. The ECL output driver circuit of claim 1 wherein the compensating current switch is an ECL compensating current switch (CCS) gate coupled between the high and low potential power rails and comprising first and second CCS gate transistors with a second common emitter node coupling, the first CCS gate transistor being coupled in the compensating current path between the ECL output gate output node and second common emitter node, and wherein the compensating current source is a second current sink coupled between the second common emitter node and low potential power rail.

4. The ECL output driver circuit of claim 3 wherein the ECL output gate comprises an emitter follower transistor output circuit coupled to the ECL output gate output node for delivering logic high and logic low potential level output signals at an output, and a temperature compensating network coupled between respective collector nodes of the first and second ECL output gate transistors and further comprising:

a stack of n voltage drop components having a negative temperature coefficient coupled between the high potential level power rail and a base node of the first ECL CCS gate transistor, and a third current sink coupled between the stack and low potential power rail for establishing a first voltage drop across the stack;

and a compensating reference voltage source coupled between the high potential power rail and a base node of the second ECL CCS gate transistor, said compensating reference voltage source being selected to provide a second voltage drop slightly greater than the first voltage drop at intermediate and high temperature ranges for normally operating the CCS gate with the first CCS gate transistor conducting a supplementary compensating current through the output voltage swing resistor coupled to the ECL output gate output node to permit low power operation of the first current sink;

said stack of voltage drop components being selected to provide a first voltage drop greater than the reference voltage source second voltage drop at a specified low temperature range of operation of the ECL output driver circuit to cut off the supplementary compensating current.

5. The ECL output driver circuit of claim 4 wherein the stack of n voltage drop components comprises a diode stack of n series coupled diodes.

6. The ECL output driver circuit of claim 5 wherein the diode stack comprises a stack of n series coupled base collector shorted (BCS) transistors providing the first voltage drop.

7. A method of operating an ECL output driver circuit for low power operation in a low temperature range, said ECL output driver circuit having an ECL output gate with first and second ECL output gate transistors with a first common emitter node coupling providing alternative collector paths through respective output voltage swing resistors according to data input signals at a base node input of one of the ECL output transistors, said ECL output gate providing an output node at the collector node of one of the ECL output gate transistors, comprising:

sinking a first current through the output voltage swing resistor in the collector current path of the first ECL gate output transistor, said output voltage swing resistor being coupled to the output node at the collector node of the first ECL gate transistor, said first current passing in a first current path through the first ECL output gate transistor and first common emitter node;

sinking a supplementary compensating second current through the output voltage swing resistor in the collector current path of the first ECL gate output transistor, and passing the second current through the output node and through a separate compensating current path to the low potential power rail in parallel with the first current path through the first ECL output gate transistor and first common emitter node, and maintaining said supplementary compensating current through said output voltage swing resistor during intermediate and high temperature operation of the ECL output driver circuit;

and switching off the supplementary compensating current through said output voltage swing resistor in a low temperature operating range of the ECL output driver circuit, said step of switching off the supplementary compensating current through said output voltage swing resistor comprising switching the supplementary compensating current in an ECL compensating current switch (CCS) gate from a first ECL CCS gate transistor coupled in the supplementary compensating current path to a second ECL CCS gate transistor coupled outside said supplementary compensating current path.

8. The method of claim 7 wherein the step of switching the supplementary compensating current in a low temperature range comprises:

coupling a stack of n voltage drop components having a negative temperature coefficient between a high potential power rail and a base node of the first ECL CCS gate transistor for defining a first voltage drop between the high potential power rail and base node of the first ECL CCS gate transistor;

providing a reference voltage source defining a reference second voltage drop between the high potential power rail and a base node of the second ECL CCS gate transistor;

and selecting the stack of n voltage drop components so that the first voltage drop is slightly less than the second voltage drop of the reference voltage source in intermediate and high temperature operating ranges of the ECL output driver circuit and so that the first voltage drop is slightly greater than the second voltage drop of the reference voltage source in a selected low temperature operating range of the ECL output driver circuit.

9. The method of claim 8 comprising the steps of providing a temperature compensating network between collector nodes of the first and second ECL output gate transistors, and supplementing bleed current provided by the temperature compensating network with said supplementary compensating current.

10. A temperature compensated ECL output driver circuit comprising an ECL output gate coupled between high and low potential power rails and having first and second ECL output gate transistors with a first common emitter node coupling providing alternative collector current paths through respective collector node output voltage swing resistors according to a data input signal at a base node input of one of the ECL output gate transistors, a first current sink coupled between the common emitter node coupling of the ECL output gate transistors and low potential power rail, at least one emitter follower transistor output circuit coupled to a collector output node of one of the ECL output gate transistors for delivering logic high and logic low potential level output signals at an output, and a temperature compensating network coupled between collector nodes of the respective ECL output gate transistors, the improvement for compensated operation of the ECL output driver circuit so that logic high output signals remain within a desired specification voltage range during operation at low power and low temperature comprising:

an ECL compensating current switch (CCS) gate comprising first and second CCS gate transistors with a second common emitter node coupling;

a second current sink coupled between said second common emitter node coupling and low potential power rail;

a diode stack of n series coupled V_BE potential drop components having a negative temperature coefficient coupled between the high potential power rail and a base node of the first ECL CCS gate transistor and a third current sink coupled between said diode stack and low potential power rail;

and a compensating reference voltage source coupled between high potential power rail and a base node of the second ECL CCS gate transistor, said compensating reference voltage source being selected to provide a voltage drop slightly greater than nV_BE at intermediate and high temperature operating ranges for formally operating the CCS gate with the first CCS gate transistor conducting a supplementary compensating current through the output voltage swing resistor at the output node of the ECL output gate to permit relatively low power operation of the first current sink;

said diode stack being selected to provide a voltage drop nV_BE greater than the reference voltage source (V1) in a specified low temperature operating range of the ECL output driver circuit to cut off the supplementary compensating current through said output voltage swing resistor in the low temperature operating range for maintaining a relatively low voltage drop across the output voltage swing resistor at the collector output node so that logic high potential level output signals remain within a desired specification voltage range during operation at low power and low temperature.

11. The ECL output driver circuit of claim 10 wherein the diode stack comprises a stack of n series coupled base collector shorted (BCS) transistors providing the negative temperature coefficient voltage drop nV_BE.

12. The ECL output driver circuit of claim 11 wherein the output voltage swing resistor at the output node is selected to have a resistance value less than approximately 1.8 times the resistance value of a tail resistor of the first current sink.

13. A temperature compensated ECL output driver circuit comprising an ECL output gate having an output voltage swing resistor coupled to an output node, the improvement for operation of the ECL output driver circuit at low power and low temperature comprising:

a compensating current source coupled to the ECL output gate output node for generating a supplementary compensating current during operation of the ECL output driver circuit in a first temperature operating range in a compensating current path through the output voltage swing resistor;

and a compensating current switch coupled in the compensating current path and constructed for switching off the supplementary compensating current during operation of the ECL output driver circuit in a specified second temperature operating range lower than the first temperature operating range, said compensating current switch being an ECL compensating current switch (CCS) gate, said compensating current source being a current sink coupled between the ECL CCS gate and a low potential power rail.

14. The ECL output driver circuit of claim 13 wherein the compensating current switch is an ECL compensating current switch (CCS) gate comprising first and second CCS gate transistors with a common emitter node coupling, the first CCS gate transistor being coupled in a compensating current path between the ECL output gate output node and common emitter node, and wherein the compensating current source is a current sink coupled between the common emitter node and a low potential power rail.

15. The ECL output driver circuit of claim 14 wherein the ECL output gate comprises an emitter follower transistor output circuit coupled to the ECL output gate output node for delivering logic high and logic low potential level output signals at an output, and further comprising:

a stack of n voltage drop components having a negative temperature coefficient coupled between a high potential level power rail and a base node of the first ECL CCS gate transistor, and a current sink coupled between the stack and low potential power rail for establishing a first voltage drop across the stack;

and a compensating reference voltage source coupled between the high potential power rail and a base node of the second ECL CCS gate transistor, said compensating reference voltage source being selected to provide a second voltage drop slightly greater than the first voltage drop at said first temperature range for normally operating the CCS gate with the first CCS gate transistor conducting a supplementary compensating current through the output voltage swing resistor coupled to the ECL output gate output node;

said stack of voltage drop components being selected to provide a first voltage drop greater than the reference voltage source second voltage drop at the specified second temperature range of operation of the ECL output driver circuit lower than the first temperature operating range to cut off the supplementary compensating current.

16. A method of operating an ECL output driver circuit for low power operation in a low temperature range, said ECL output driver circuit comprising an ECL output gate having an output voltage swing resistor coupled to an output node, comprising:

sinking a first current through the output voltage swing resistor and output node in a first current path of the ECL output gate;

sinking a supplementary compensating second current through the output voltage swing resistor, and passing the second current through the output node and through a separate compensating current path to a low potential power rail in parallel with the first current path through the first ECL output gate, and maintaining said supplementary compensating current through said output voltage swing resistor during a first operating temperature range of the ECL output driver circuit;

and switching off the supplementary compensating current through said output voltage swing resistor in a second temperature operating range of the ECL output driver circuit lower than the first operating temperature range, said step of switching off the supplementary compensating current through said output voltage swing resistor comprising switching the supplementary compensating current in an ECL compensating current switch (CCS) gate from a first ECL CCS gate transistor coupled in the supplementary compensating current path to a second ECL CCS gate transistor coupled outside said supplementary compensating current path.

17. The method of claim 16 wherein the step of switching the supplementary compensating current in a low temperature range comprises:

coupling a stack of n voltage drop components having a negative temperature coefficient between a high potential power rail and a base node of the first ECL CCS gate transistor for defining a first voltage drop between the high potential power rail and base node of the first ECL CCS gate transistor;

providing a reference voltage source defining a reference second voltage drop between the high potential power rail and a base node of the second ECL CCS gate transistor;

and selecting the stack so that the first voltage drop is slightly less than the second voltage drop of the reference voltage source in the first temperature operating range of the ECL output driver circuit and so that the first voltage drop is slightly greater than the second voltage drop of the reference voltage source in the second temperature operating range of the ECL output driver circuit.