Sigma-delta digital-to-analog converter with reduced noise

• US 5,323,157 A
• Filed: 01/15/1993
• Issued: 06/21/1994
• Est. Priority Date: 01/15/1993
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Irwin, James S., Ledzius, Robert C.
• Primary Examiner(s): Hoff, Marc S.
• Application Number:
  US08/004,816
• Time in Patent Office: 522 Days
• Field of Search: 341/118, 341/136, 341/143, 341/144, 364/724.16, 364/825
• US Class Current: 341/143
• CPC Class Codes: H03M 3/504 the final digital/analogue converter being constituted by a finite impulse response [FIR] filter, i.e. FIRDAC

Abstract

A sigma-delta digital-to-analog converter (DAC) (40) receives oversampled input data representative of an analog signal. The data may be optionally interpolated to a higher rate in a interpolator (41). A noise-shaping sigma-delta modulator (42) is connected to the output of the interpolator (41). The output of the modulator (42) is provided to a finite impulse response (FIR) filter (43). The FIR filter (43) has a frequency response characteristic which reduces the shaped noise and aliased components. This noise has a tendency to intermodulate back into the DAC'"'"'s passband. The FIR filter (43) uses a series of flip-flops (81, 82, 83) functioning as delay elements with well-controlled timing edges. The outputs of the flip-flops (81, 82, 83) control current sources (91, 92, 93) weighted according to corresponding filter coefficients. The outputs of the current sources (91, 92, 93) are then summed in a summing device such as an amplifier (101).

Claims

1. A sigma-delta digital-to-analog converter with reduced noise comprising:

a sigma-delta modulator having n input for sequentially receiving first digital data words, a clock input terminal for receiving a modulator clock signal, and an output terminal for providing a modulator output signal having a value in a passband of the digital-to-analog-converter corresponding to said first digital data words; and

a finite impulse response (FIR) filter having an input coupled to said output terminal of said sigma-delta modulator, and an output for providing an analog signal;

said FIR filter shaping said second analog signal according to a predetermined transfer function, thereby decreasing intermodulated noise in said passband of the sigma-delta digital-to-analog converter, wherein said FIR filter comprises;

a plurality of delay elements ordered from a first delay element to a last delay element, said first delay element having an input for receiving said modulator output signal, each delay element besides said first delay element having an input coupled to an output of a preceding delay element, each delay element delaying an input thereof by one period of said modulator clock to provide a delayed signal at an output thereof;

a plurality of amplifier means corresponding to each of said plurality of delay elements, each amplifier means having an input coupled to an output of a corresponding one of said plurality of delay elements, and an output, said plurality of delay elements having gains to implement said predetermined transfer function, wherein each of said amplifier means comprises a controlled current source; and

a summing device having inputs coupled to each of said output terminals of said plurality of delay elements, and an output terminal for providing said analog signal.

2. The sigma-delta digital-to-analog converter of claim 1 wherein said predetermined transfer function comprises a Hamming window.

3. The sigma-delta digital-to-analog converter of claim 1 wherein each controlled current source is characterized as being a cascode current source.

4. The sigma-delta digital-to-analog converter of claim 1 wherein each controlled current source comprises:

a first transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode for receiving a bias voltage, and a second current electrode;

a second transistor having a first current electrode coupled to said second current electrode of said first transistor, a control electrode coupled to second first current electrode of said first transistor, and a second current electrode coupled to a second power supply voltage terminal;

a third transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode coupled to said first power supply voltage terminal, and a second current electrode;

a fourth transistor having a first current electrode coupled to said second current electrode of said third transistor, a control electrode coupled to said second current electrode of said first transistor, and a second current electrode coupled to said second power supply voltage terminal;

a fifth transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode coupled to an output of a corresponding delay element, and a second current electrode;

a sixth transistor having a first current electrode coupled to said second current electrode of said fifth transistor, a control electrode coupled to said first current electrode of said first transistor, and a second current electrode coupled to said second power supply voltage terminal; and

a seventh transistor having a first current electrode for providing an output of said controlled current source, a control electrode coupled to said second current electrode of said third transistor, and a second current electrode coupled to said second current electrode of said fifth transistor.

5. The sigma-delta digital-to-analog converter of claim 4 wherein said first transistor is a P-channel MOS transistor, and wherein said second, third, fourth, fifth, sixth, and seventh transistors are N-channel MOS transistors.

6. A sigma-delta digital-to-analog converter with reduced noise comprising:

noise-shaping means for sequentially receiving first digital data words at a first clock frequency, for shaping quantization noise in said first digital data words out-of-band, and for providing an output signal having an in-band component substantially equal to an analog representation of said first digital data words; and

a finite impulse response (FIR) filter having an input for receiving said output signal of said noise-shaping means, and an output for providing an analog signal as an output of the sigma-delta digital-to-analog converter;

said FIR filter shaping said analog signal according to a predetermined transfer function, thereby decreasing intermodulated noise in said passband of the sigma-delta digital-to-analog converter;

said FIR filter implementing a Hamming window.

7. A sigma-delta digital-to-analog converter with reduced noise comprising:

a sufficiently-resolved sigma-delta modulator having an input for receiving first digital data words, a clock input terminal for receiving a modulator clock signal, and an output terminal for providing an output having a plurality of bits including first and second bits;

said first output bit corresponding to a most-significant bit of said output;

said second bit corresponding to a tap bit which is not said most significant or a second most-significant bit of said output;

a first finite impulse response (FIR) filter having an input for receiving said first output bit, and an output for providing a first analog output signal;

a second FIR filter having an input for receiving said second output bit, and an output for providing a second analog signal;

means for weighting an output of said second FIR filter according to a relative significance of said second output bit compared to said first output bit; and

summing means coupled to said first and second FIR filters, for summing said first and second analog output signals to provide a third analog output signal which is an output sigma of the sigma-delta digital-to-analog converter;

said first and second FIR filters filtering said first and second bits, respectively, according to predetermined transfer functions, thereby decreasing a potential for intermodulated noise in said passband of the sigma-delta digital-to-analog converter.

8. The sigma-delta digital-to-analog converter of claim 7 wherein said sufficiently-resolved sigma-delta modulator is characterized as being a second-order sigma-delta modulator.

9. The sigma-delta digital-to-analog converter of claim 7 further comprising an interpolator having an input for sequentially receiving second data words at a second clock frequency, and an output for providing said first data words at said first frequency.

10. The sigma-delta digital-to-analog converter of claim 7 wherein each of said first FIR filter and said second FIR filter implements a Hamming window.