Semiconductor SRAM with trench transistors

• US 5,324,973 A
• Filed: 05/03/1993
• Issued: 06/28/1994
• Est. Priority Date: 05/03/1993
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Sivan, Richard D.
• Primary Examiner(s): LIMANEK, ROBERT P
• Application Number:
  US08/055,582
• Time in Patent Office: 421 Days
• Field of Search: 257/330, 257/331, 257/332, 257/334, 257/301, 257/302, 257/903, 257/904, 257/393, 365/154
• US Class Current: 257/330
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

A semiconductor memory cell (10) includes vertically disposed MOS pass transistors (32, 34) and MOS inverters (12, 14) contained in trench structures in a semiconductor substrate (11). An MOS inverter (12) has a toroidal shared-gate electrode (48) overlying the wall surface of a first trench (36). A pass transistor (32) has a gate electrode (84) in a third trench (40). A first buried drain region (62) resides in the substrate (11) adjacent to the first trench (36), and is located a first distance from the substrate surface. A second buried drain region (64) resides in the substrate (11) adjacent to the second trench (32), and is located a second distance from the substrate surface. The inverter (12) and the pass transistor (32) are electrically coupled by the first and second buried layers (62, 64). The channel length (90) of the driver transistor (16) in the inverter (12) and the pass transistor (32) is determined by the first and second distances, respectively. Accordingly, the cell ratio of the memory cell (10) (ratio of W/L values) is also determined by the differential depth of the first and second buried drain regions (62, 64).

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a surface;

first and second trenches in the substrate;

a first MOS transistor in the first trench, the MOS transistor having a first buried, drain region adjacent to the first trench;

a second MOS transistor in the second trench, the second MOS transistor having a second, buried drain region adjacent to the second trench; and

an electrically-conductive interconnect layer filling a central portion of the second trench and extending onto the surface of the substrate,

wherein the second buried drain region electrically couples the interconnect layer to the first buried drain region, and

wherein the first buried drain region is located a first distance from the substrate surface, and the second buried drain region is located a second distance from the substrate surface, and wherein the second distance is less than the first distance.

2. The semiconductor device of claim 1 further comprising:

a third trench in the semiconductor substrate; and

a third MOS transistor in third trench, the third MOS transistor having a gate electrode extension overlying a portion of the substrate surface adjacent to the third trench;

wherein the interconnect layer electrically contacts the gate electrode extension.

3. A semiconductor device comprising:

a semiconductor substrate having a surface;

a first and second trenches in the substrate, each trench having a wall surface;

a first drain region at the surface of the substrate adjacent to the first trench;

a second drain region at the surface of the substrate adjacent to the second trench;

a first buried drain region in the substrate adjacent to the first trench and located a first distance from the first drain region; and

a second buried drain region in the substrate adjacent to the second trench and located a second distance from the second drain region,

wherein the second buried drain region electrically contacts the first buried drain region, and

wherein the second distance is less than the first distance.

4. The semiconductor device of claim 3 further comprising:

a first channel region adjacent to the wall surface of the first trench, and corresponding to the first distance;

a first gate electrode in the first trench and electrically isolated from the first channel region by a gate dielectric layer;

a second channel region adjacent to the wall surface of the second trench, and corresponding to the second distance; and

a second gate electrode in the second trench and electrically isolated from the second channel region by the dielectric layer.

5. The semiconductor device of claim 4 further comprising:

an electrically conductive interconnect layer electrically isolated from the first gate electrode and electrically contacting the first drain region.

6. A semiconductor device comprising:

a semiconductor substrate having a surface;

first and second trenches in the substrate;

a first MOS inverter in the first trench and a second MOS inverter in the second trench,

wherein each inverter has a toroidal, shared-gate electrode;

a first gate extension integral with the first shared-gate electrode;

a second gate extension integral with the second shared-gate electrode;

a thin-film channel layer overlying and electrically isolated from the shared-gate electrode of each inverter;

an interconnect layer filling a central portion of each trench,

wherein the interconnect layer in the first trench electrically couples the thin-film channel layer in the first trench to the second gate extension, and

wherein the interconnect layer in the second trench electrically couples the thin-film channel layer in the second trench to the first gate extension;

a third trench in the semiconductor substrate;

an MOS transistor in the third trench, the MOS transistor having a first buried drain region adjacent to the third trench;

a second buried drain region in the substrate adjacent to the first trench,

wherein the second buried drain region electrically couples the first buried drain region to the thin-film channel layer in the first trench; and

wherein the first buried drain region is located a first distance from the substrate surface, and the second buried drain region is located a second distance from the substrate surface, and wherein the second distance is less than the first distance.

7. The semiconductor device of claim 6, wherein the MOS transistor further comprises:

a first drain region located at the surface of the substrate and adjacent to the third trench;

a gate electrode in the third trench and electrically isolated from the substrate; and

a second interconnect layer electrically isolated from the gate electrode and electrically contacting the first drain region.

8. A semiconductor device comprising:

a semiconductor substrate having a surface;

first and second trenches in the substrate;

a first vertically disposed MOS transistor in the first trench;

a second vertically disposed MOS transistor in the second trench, wherein the second MOS transistor is electrically coupled to the first MOS transistor;

a first buried drain region of the first MOS transistor in the substrate adjacent to the first trench and located a first distance from the substrate surface; and

a second buried drain region of the second MOS transistor in the substrate adjacent to the second trench and located a second distance from the substrate surface, wherein the first distance is greater than the second distance, and

whereby the second transistor has a substantially higher current gain than the first transistor.