Nitride capped MOSFET for integrated circuits

• US 5,324,974 A
• Filed: 04/14/1993
• Issued: 06/28/1994
• Est. Priority Date: 09/04/1990
• Status: Expired due to Term

• Current Assignee: Acer, Inc.
• Original Assignee: Industrial Technology Research Institute
• Inventors: Liao, I-Chi
• Primary Examiner(s): Crane, Sara W.
• Assistant Examiner(s): GUAY, JOHN FRANCIS
• Application Number:
  US08/046,781
• Time in Patent Office: 440 Days
• Field of Search: 257/412, 257/413, 257/408, 257/900, 257/639, 257/640, 257/344
• US Class Current: 257/344
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A method is described for fabricating a lightly doped drain MOSFET integrated circuit device. The method begins by forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide, a polysilicon layer and a refractory metal silicide. A thin silicon nitride layer is formed over each of the structures and the exposed surfaces therebetween of the substrate. A pattern of lightly doped regions in the substrate is formed by ion implantation using the polycide gate structures as the mask. A dielectric spacer structure is formed upon the sidewalls of each of the polycide gate structures and over the adjacent portions of the substrate. A pattern of heavily doped regions in the substrate is formed by ion implantation using the polycide structures with spacer structures as the mask to produce the lightly doped drain source/drain structures of an MOSFET device. The integrated circuit device is completed by forming a passivation layer over the structures described and appropriate electrical connecting structures thereover to electrically connect the gate electrode structures and source/drain elements.

Claims

1. A lightly doped drain MOS FET integrated circuit device comprising:

a pattern of gate electrode structures upon a semiconductor substrate which structures each have vertical sidewalls and includes a gate oxide, a polysilicon layer and a refractory metal silicide;

a first thin silicon nitride layer with a thickness in the range of 80 to 300 Angstroms over said each of said gate electrode structures, including said vertical sidewalls, and over the surface of said substrate;

a pattern of lightly doped regions in said substrate adjacent to said structures;

a dielectric spacer structure upon the sidewalls of each of said structures and over the adjacent portions of said substrate;

a pattern of heavily doped regions in said substrate adjacent to said dielectric spacer structure on the vertical sidewalls of said gate electrode structures, which form lightly doped drain source/drain structures of an MOS FET device;

a passivation layer over the said structures and appropriate electrical connecting structures thereover to electrically connect the said structure gate electrode structures and source/drain elements to form said integrated circuit device; and

wherein a second thin silicon nitride layer is formed over said spacer structures and over said substrate, and said passivation layer is formed over said second thin silicon nitride layer.

2. The integrated circuit device of claim 1 wherein said passivation layer is a heat smoothed borosilicate glass layer having a thickness of between about 5000 to 10000 Angstroms.

3. The integrated circuit device of claim 1 wherein said first thin silicon nitride layer remains a part of the resulting device under the said dielectric spacer structures and said second thin silicon nitride layer remains a part of the resulting integrated circuit device.

4. The integrated circuit device of claim 1 wherein a thin silicon dioxide layer less than about 100 Angstroms in thickness is located under the said first thin silicon nitride layer and the thickness of said second thin silicon nitride layer is less than about 300 Angstroms.

5. The integrated circuit device of claim 1 wherein the said refractory metal silicide is tungsten silicide, the thickness of said tungsten silicide layer is between about 1000 and 3000 Angstroms and the thickness of the said polysilicon layer is between about 1000 and 3000 Angstroms.