Field effect transistor device with contact in groove

• US 5,324,981 A
• Filed: 04/14/1993
• Issued: 06/28/1994
• Est. Priority Date: 07/01/1988
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Yoshida, Masahiro, Ishikawa, Takahide, Kobiki, Michihiro
• Primary Examiner(s): LARKINS, WILLIAM
• Application Number:
  US08/046,920
• Time in Patent Office: 440 Days
• Field of Search: 357/22, 357/49, 357/53, 357/55, 257/276, 257/630, 257/620, 257/621
• US Class Current: 257/276
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 148/028 Dicing
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A high power FET device includes a plated heat sink, a rear surface electrode disposed between a substrate and the heat sink, a via-hole extending through the substrate and containing a metal plating for electrically connecting the rear surface electrode and an element, such as the source electrode, of the FET device. A metallic layer extending from the rear surface to the front surface of the device protects the side walls of the substrate during handling. The side wall protection layer extends onto portions of the front surface of the substrate as a measurement electrode. The arrangement gives access to the source, drain, and gate electrodes of the device from the front surface for measuring the electrical characteristics of the device while it is still part of a wafer containing a large number of devices. Each device includes a separation groove outwardly spaced from the device and containing a metallic layer which becomes the side wall protection layer after dicing. Preferably, the separation grooves are wider and deeper than the via-holes.

Claims

1. A semiconductor device assembly comprising:

a semiconductor wafer having opposed front and rear surfaces, said wafer being a common substrate;

a plurality of substantially identical semiconductor devices formed on said wafer, each device including at least one via-hole extending into said wafer from said front surface toward said rear surface;

at least one circumferential separation groove extending into said wafer from said front surface toward said rear surface farther than said at least one via-hole and lying outwardly from a first of said semiconductor devices for separation of said first semiconductor device from said wafer;

a first metallic electrode disposed in said at least one via-hole for electrically connecting said respective semiconductor devices at said front surface; and

a metal layer disposed in said at least one separation groove for forming a metal protection layer on surfaces of said semiconductor devices when they are separated from said wafer.

2. The semiconductor device assembly of claim 1 wherein said at least one separation groove is wider than said at least one via-hole.

3. The semiconductor device assembly of claim 1 wherein said first metallic electrode and said metal layer are gold.

4. The semiconductor device assembly of claim 1 wherein said metal layer extends over portions of the front surface of said first semiconductor device from said at least one separation groove to form a measurement electrode for measuring electrical characteristics of said first semiconductor device before its separation from said wafer.

5. The semiconductor device assembly of claim 4 including a second metallic electrode disposed on the rear surface of said substrate in electrical communication with said first metallic electrode at said at least one via-hole and with said metal layer.

6. The semiconductor device assembly of claim 5 including a plated heat sink disposed on said second metallic electrode.

7. The semiconductor device assembly of claim 1 wherein said semiconductor devices are field effect transistors, each including an active region in said wafer at said front surface and a source electrode, a drain electrode, and a gate electrode disposed on said front surface at said active region.

8. The semiconductor device assembly of claim 7 wherein said gate electrode forms a Schottky barrier with said active region and said source and drain electrodes form ohmic contacts with said active region.

9. The semiconductor device assembly of claim 1 wherein said wafer is GaAs.