Neuron unit and neuron unit network

• US 5,324,991 A
• Filed: 12/11/1992
• Issued: 06/28/1994
• Est. Priority Date: 07/12/1989
• Status: Expired due to Term

• Current Assignee: Ricoh Company Limited
• Original Assignee: Ricoh Company Limited
• Inventors: Oteki, Sugitaka, Otsuki, Satoshi, Aono, Eiki, Watanabe, Takahiro, Eguchi, Hirotoshi, Tsukagoshi, Toshihiro, Furuta, Toshiyuki, Horiguchi, Hiroyuki, Motomura, Shuji, Hashimoto, Atsuo
• Primary Examiner(s): Hudspeth, David R.
• Application Number:
  US07/989,605
• Time in Patent Office: 564 Days
• Field of Search: 307/201, 395/25-27
• US Class Current: 706/41
• CPC Class Codes: G06N 3/063 using electronic means

Abstract

A neuron unit processes a plurality of binary input signals and outputs a neuron output signal which is indicative of a result of the processing. The neuron unit is provided with a plurality of first gates respectively for carrying out a logical operation on a binary input signal and a weighting coefficient, a second gate for carrying out a logical operation on an excitatory output signal of each of the first gates, a third gate for carrying out a logic operation on an inhibitory output signal of each of the first gates, a fourth gate for synthesizing output signals of the second and third gates and outputting the neuron output signal, and a generating circuit for generating the weighting coefficients which are supplied to each of the first gates. The generating circuit for generating one weighting coefficient includes a random number generator for generating random numbers, and a comparator for comparing each random number r with a predetermined value q and for outputting a pulse signal having first and second values depending on whether each random number r is such that r≦q or r>q, and each weighting coefficient is described by a pulse density.

Claims

1. A neuron unit for processing a plurality of binary input signals and for outputting a neuron output signal which is indicative of a result of the processing, said neuron unit comprising:

a plurality of first gate means, respectively for carrying out a logical operation on a binary input signal and a weighting coefficient;

a second gate means, coupled to said first gate means, for carrying out a logical operation on an excitatory output signal of each of said first gate means;

a third gate means, coupled to said first gate means, for carrying out a logic operation on an inhibitory output signal of each of said first gate means;

a fourth gate means, coupled to said second and third gate means, for synthesizing output signals of said second and third gate means and outputting the neuron output signal; and

generating means, coupled to said first gate means, for generating the weighting coefficients which are supplied to each of said first gate means,

said generating means for generating one weighting coefficient including a random number generator for generating random numbers, and a comparator for comparing each random number r output from the random number generator with a predetermined value r and for outputting a pulse signal having first and second values depending on whether each random number r is such that r≦

q or r>

q,

each weighting coefficient being described by a pulse density which is defined by at least one of a number of the first values and a number of the second values of the pulse signal within a predetermined time, where the first and second values are arranged at random and the first and second values respectively correspond to high and low binary signal levels.

2. The neuron unit as claimed in claim 1, wherein said generating means further includes a register for storing the predetermined value q.

3. The neuron unit as claimed in claim 1, wherein the random number generator of said generating means includes a linear feedback shift register which successively shifts bits of an initial value set therein in response to clock pulses.

4. The neuron unit as claimed in claim 1, wherein the random number generator of said generating means includes an n-bit shift register having an input part for successively shifting bits of an initial value set therein in response to clock pulses, an exclusive-OR circuit for obtaining an exclusive-OR of two arbitrary ones of n outputs of the shift register, and a switching circuit for selectively outputting one of an output of the exclusive-OR circuit and an arbitrary one of the n outputs of the shift register in response to a control signal, said switching circuit supplying an output thereof to the input part of the shift register.

5. The neuron unit as claimed in claim 1, wherein the random number generator of said generating means includes an n-bit shift register having an input part for successively shifting bits of an initial value set therein in response to clock pulses, a switching circuit for selectively outputting one of two arbitrary ones of n outputs of the shift register in response to a control signal, and an exclusive-OR circuit for obtaining an exclusive-OR of an arbitrary one of the n outputs of the shift register and an output of the switching circuit, said exclusive-OR circuit supplying an output thereof to the input part of the shift register.

6. The neuron unit as claimed in claim 1, wherein the random number generator of said generating means includes a linear feedback shift register having an input part, and output control means, coupled to the linear feedback shift register, for operating to block an output of the linear feedback shift register if a number of clock pulses counted by the linear feedback shift register reaches M until N more clock pulses are input to the linear feedback shift register, where M denotes a number of clock pulses required to generate pulses from the linear feedback shift register amounting to one period of a maximum length linearly recurring sequence signal, and N denotes a predetermined number such that N<

M.

7. The neuron unit as claimed in claim 6, wherein the random number generator of said generating means further includes a means for changing the value N every time the output control means operates.

8. The neuron unit as claimed in claim 1, wherein the random number generator of said generating means includes an n-bit shift register having an input part for successively shifting bits of an initial value set therein in response to clock pulses, an exclusive-OR circuit for obtaining an exclusive-OR of a fixed one of n outputs of the shift register and an arbitrary one of n outputs of the shift register, and selector means for selecting the arbitrary one of the n outputs of the shift register to a different one of the n outputs every time a random pulse sequence is output from the shift register for a predetermined time, said exclusive-OR circuit supplying an output thereof to the input part of the shift register.

9. The neuron unit as claimed in claim 8, wherein the selector means of said generating means includes a counter for counting pulses of a predetermined signal, and a selector, coupled to the counter and specific ones of the n outputs of the shift register, for selectively supplying one of the specific ones of the n outputs depending on a counted value of the counter.

10. The neuron unit as claimed in claim 8, wherein the selector means of said generating means includes an m-bit shift register for shifting pulses of a predetermined signal, and a selector, coupled to the m-bit shift register and specific ones of the n outputs of the n-bit shift register, for selectively supplying one of the specific ones of the n outputs depending on a value stored in the m-bit shift register.

11. The neuron unit as claimed in claim 8, wherein the selector means of said generating means includes a linear feedback shift register for shifting pulses of a predetermined signal, and a selector, coupled to the linear feedback shift register and specific ones of the n outputs of the n-bit shift register, for selectively supplying one of the specific ones of the n outputs depending on an output value of the linear feedback shift register.

12. The neuron unit as claimed in claim 1, wherein the random number generator of said generating means includes first means for generating random pulses corresponding to the random numbers in response to clock pulses, and said generating means further includes:

second means for counting the random pulses output from said first means,

third means for comparing a counted value of the second means with a preset value, and

blocking means for blocking the clock pulses from being supplied to the first means depending on a comparison result of the third means.

13. The neuron unit as claimed in claim 12, wherein the said first means includes a linear feedback shift register which successively shifts bits of an initial value set therein in response to the clock pulses, and said generating means further includes fourth means for changing the initial value set in the linear feedback shift register when a number of the clock pulses supplied to the random number generator reaches a number required for said first means to generate the random pulses amounting to one period thereof.

14. The neuron unit as claimed in claim 1, wherein the random number generator of said generating means includes:

a plurality of linear feedback shift registers responsive to clock pulses,

switching means, coupled to the linear feedback shift registers, for connecting the linear feedback shift registers to form a single shift register in a first mode and for disconnecting the linear feedback shift registers into independent registers in a second mode, and

bit generating means, coupled to the single shift register, for generating at least one bit,

an initial value being set in each of the linear feedback shift registers when the switching means switches to the second mode after the bit from the bit generating means is transferred to the single shift register during the first mode of the switching means.

15. The neuron unit as claimed in claim 14, wherein the bit generating means includes a linear feedback shift register having a predetermined number of stages, and each linear feedback shift register of the random number generator has a number of stages greater than the predetermined number.