Generic control unit

• US 5,325,043 A
• Filed: 07/08/1992
• Issued: 06/28/1994
• Est. Priority Date: 11/07/1989
• Status: Expired due to Fees

• Current Assignee: Sundstrand Corporation (Raytheon Technologies Corporation d/b/a RTX)
• Original Assignee: Sundstrand Corporation (Raytheon Technologies Corporation d/b/a RTX)
• Inventors: Parro, Bob
• Primary Examiner(s): HICKEY, ROBERT
• Application Number:
  US07/910,671
• Time in Patent Office: 720 Days
• Field of Search: 322/25, 322/27, 322/28, 322/23, 322/29, 320/64, 361/20
• US Class Current: 322/23
• CPC Class Codes: H02P 2101/30 for aircraft
• CPC Class Codes: H02P 9/42 to obtain desired frequency without varying speed of the generator

Abstract

The problems of minimizing size and weight in an aircraft and avoiding requirements for custom design are minimized in a generator control unit (22) provided with separate digital control circuits (74 and 76) for implementing voltage regulation and speed control. These circuits (74 and 76) are manufactured using custom very large scale integration (VLSI) technology to reduce size, weight, life cycle costs and improve reliability.

Claims

1. A generator control unit for an electrical power generating system (EPGS) having a generator, a drive for the generator, and fault control means connecting said generator in the EPGS for protecting the EPGS under fault conditions, the generator control unit comprising:

a control circuit including means responsive to system condition inputs for controlling generator operation to maintain generator output power at a desired voltage level and frequency, wherein said control circuit includes first and second digital control circuits for developing respective first and second control signals for controlling generator output voltage and generator speed, each digital control circuit comprising a processor which develops the respective control signal in accordance with an algorithm including at least one gain and compensation function and a memory associated with the processor and storing algorithm and gain and compensation variables for retrieval by the processor in performing the algorithm; and

a protection circuit including a processor responsive to system condition inputs for controlling operation of said fault control means, and a digital interface circuit providing a communication interface between said processor and the system condition inputs and between said processor and said fault control means, wherein said protection circuit processor is connected with said first and second digital control circuits for loading said variables into said memories.

2. The generator control unit of claim 1 wherein said protection circuit processor loads the one algorithm into said memories.

3. A generator control unit for an electrical power generating system (EPGS) having a generator, with means responsive to a first control signal for varying generator output power, a drive for the generator, with means responsive to a second control signal for varying the generator speed, and fault control means connecting said generator in the EPGS for protecting the EPGS under fault conditions, the generator control unit comprising:

a control circuit including means responsive to system condition inputs for developing said first and second control signals to maintain generator output power at a desired voltage level and frequency, said control circuit including first and second digital control circuits for developing said first and second control signals, respectively, wherein said first and second digital control circuits each comprise a processor which develops the respective control signal in accordance with an algorithm including at least one gain and compensation function and a memory connected with the processor and storing said algorithm and gain and compensation function variables for retrieval by the processor in performing the algorithm;

a protection circuit including a processor responsive to system condition inputs for controlling operation of said fault control means, wherein said protection circuit processor is connected with said first and second digital control circuits for loading said variables into said memories;

a first analog circuit operatively associated with said control circuit providing a signal conditioning interface between said developing means and the system condition inputs; and

a second analog circuit operatively associated with said protection circuit providing a signal conditioning interface between said processor and the system condition inputs.

4. The generator control unit of claim 3 wherein said protection circuit processor loads the one algorithm into said second digital control circuit'"'"'s memory.