Method and apparatus for integrated circuit diagnosis

• US 5,325,309 A
• Filed: 04/30/1991
• Issued: 06/28/1994
• Est. Priority Date: 04/30/1991
• Status: Expired due to Term

• Current Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Shastry, Nanjunda, Halaviati, Ramin
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US07/694,291
• Time in Patent Office: 1,155 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/578, 395/157, 395/160, 371/22.3
• US Class Current: 703/15
• CPC Class Codes: G01R 31/305 using electron beams investigating or analysing materials by measuring photoelectric effect G01N23/227

Abstract

A technique for pinpointing and analyzing failures in complex integrated circuits is disclosed. A tester stimulates the a device (DUT) with input patterns. DUT output patterns are communicated back to the tester, and are compared to simulation results. Failing outputs are identified. Working back from the failing output, suspect failing nodes are identified in a schematic editor. Through a layout database linked to the schematic editor, the position of each suspect failing node is identified. A probe and SEM are positioned at nodes suspected of causing the failure. Live waveforms generated by the probe are compared with simulated waveforms for the node, while the DUT is being re-exercised by the tester. In a windowed display environment, the user is provided with schematic, layout, SEM image, and live and simulated waveforms for the suspect node. Node after node are explored in this manner until the failing circuit element is identified. Documentation is provided by printing any and all of the windows.

Claims

1. An integrated system for simulating and analyzing designs of, and for exercising and probing physical implementations of complex circuits comprising:

a schematic editor component of the integrated system for navigating through a design of a circuit, said schematic editor including means for selecting nets of the design,

a logic simulator component of the integrated system for providing simulated waveforms at the nets of the design selected in the schematic editor and for providing a set of I/O test vectors,

a layout program component of the integrated system providing a net-list level circuit layout of the design;

a tester component of the integrated system for applying the test vectors to external nodes of a physical implementation of the design;

a probe component of the integrated system for measuring live waveforms at a specific node on the physical implementation of the design;

a software layer component of the integrated system, including a user interface and a programmatic interface, linking the schematic editor component to the probe component;

means for positioning the probe in response to nets selected on the schematic editor to measure the live waveform at nodes corresponding to the selected nets;

an interface component of the integrated system for synchronizing operation of the schematic editor, logic simulator, tester, and probe components;

means for displaying in the integrated system the live waveforms and the simulated waveforms corresponding to the selected nets, in real time and side-by side with one another on a single display screen.

2. An integrated system for simulating and analyzing designs of, and for exercising and probing physical implementations of complex circuits, according to claim 1, further comprising:

means for comparing the simulated and live waveforms for the selected nets.

3. A method of diagnosing integrated circuits, comprising:

a) selecting one or more nets of interest on a display of a schematic diagram;

b) highlighting the selected nets on a display and automatically positioning a probe at a corresponding area on a device under test;

c) probing the selected net on the DUT with an e-beam;

d) displaying a live waveform for the selected net;

e) storing the live waveform;

f) simulating a waveform for the selected net;

g) displaying the simulated waveform; and

h) comparing the simulated and live waveforms;

wherein the steps of probing the selected net, displaying the live waveform and storing the live waveform include;

providing a set of stimuli to external pins of the DUT, said stimuli corresponding to patterns of stimuli applied when simulating the waveform for the selected net;

instructing the probe to sample the live waveform at the corresponding area on the DUT such that the live waveform corresponds in time to the simulated waveform; and

retrieving the live waveform from the probe tool and storing it in a memory.

4. A method of testing integrated circuits, comprising:

(a) providing a schematic design of an integrated circuit on an ECAD system;

(b) providing a set of test vectors on the ECAD system for the integrated circuit, said test vectors corresponding to waveforms to be applied to external input nodes of the integrated circuit;

(c) providing, on the ECAD system, a set of expected results corresponding to waveforms expected to be observed at external output nodes (pins) of the integrated circuit when exercised according to the test vectors;

(d) providing a physical implementation of the integrated circuit as a device under test (DUT);

(e) exercising the DUT according to the test vectors;

(f) detecting a faulty external output node of the DUT for which output signals resulting from step (e) differ from the expected results;

(g) generating a list of internal DUT circuit elements associated with each of the faulty external output node for probing;

(h) re-exercising the DUT;

(i) probing a circuit element on the DUT from the list of circuit elements while re-exercising the inputs;

(j) viewing live waveforms from the element being probed in step (i);

(k) viewing simulated waveforms for the element being probed;

(l) comparing the simulated waveforms (step (k) and the live waveforms (step (j)); and

(m) repeating the steps (h) through (l), element by element, until a faulty element is located.

5. A method according to claim 4, further comprising:

(n) repeating the steps (h) through (m) until every element in the list of elements has been probed.