Dual port semiconductor memory device

• US 5,325,332 A
• Filed: 10/05/1992
• Issued: 06/28/1994
• Est. Priority Date: 10/03/1991
• Status: Expired due to Term

• Current Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Original Assignee: NEC Corporation
• Inventors: Tagaya, Mitsue
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): NIRANJAN, FRANK
• Application Number:
  US07/956,244
• Time in Patent Office: 631 Days
• Field of Search: 365/200, 365/230.05, 365/230.06
• US Class Current: 365/200
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: G11C 29/20 using counters or linear-feedback shift registers [LFSR]
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells

Abstract

A dual-port RAM according to the present invention includes means responsive to a first control signal for determining at an input of a counter whether or not a redundancy substitution is required during a time period for which a serial read out is performed, outputting a result of the determination as a second control signal and holding the second control signal. Therefore, the determination of necessity of redundancy substitution can be performed at a timing prior to the conventional serial read by one serial read cycle. Further, since there are a plurality of read data buses provided, an interleave read out becomes possible. Therefore, a time from the determination of necessity of substitution to the redundancy circuit to an execution of substitution is also shortened by one serial read cycle, resulting in a speed up of the serial read.

Claims

1. A dual-port semiconductor memory comprising:

a memory cell array including a plurality of memory cells arranged in row and column directions, a plurality of bit lines each connecting these memory cells in a row commonly and a plurality of word lines each connecting the memory cells in a column commonly;

a row address decoder responsive to a row address signal to select one of the bit lines;

a column address decoder responsive to a column address signal to select one of the word lines;

at least two redundancy memory cells;

a serial selector circuit for selecting the memory cells serially in synchronism with a first control signal;

a defective address memory circuit for storing a location of a defective memory cell among the memory cells;

a counter having an output corresponding to a memory cell address selected by said serial selector circuit and adapted to be incremented in response to the first control signal;

a coincidence detection circuit for comparing an input signal of said counter with an output of said defective address memory circuit and outputting a second control signal for substituting said two redundancy memory cells for said memory cells corresponding to at least two of said bit lines when said input signal of the counter coincides with said output of the defective address memory circuit;

means for receiving an initial address corresponding to an external address signal code word;

wherein said serial selector circuit comprises a data register having a plurality of memory stages, a data transfer circuit for connecting the memory cells to the data register, a plurality of read data buses, a column selector circuit for connecting the data register to the read data buses, and a shift register having a plurality of outputs for control of said column selector circuit and incremented with the initial address;

a D-F/F circuit for holding said output of said coincidence detection circuit; and

a read data bus selector circuit responsive to said counter for selecting one of said plurality of read data buses, wherein an output of said read data bus selector circuit is a clock signal of said D-F/F circuit.

2. A dual-port semiconductor memory comprising:

a memory cell array including a plurality of memory cells arranged in row and column directions, a plurality of bit lines each connecting the memory cells in a row commonly and a plurality of word lines each connecting the memory cells in a column commonly;

a column address decoder responsive to a column address signal to select one of the bit lines;

a row address decoder responsive to a row address signal to select one of the word lines;

at least one redundancy memory cell;

a serial selector circuit for selecting the memory cells serially in synchronism with a first control signal;

a defective address memory circuit for storing a location of a defective memory cell among the memory cells on a memory chip;

means for receiving an initial address corresponding to an external address signal code word;

a coincidence detection circuit for incrementing the initial address corresponding to an address signal code word of said address signal in synchronism with a transfer signal, comparing the incremented address with an output of the defective address memory circuit and outputting a second control signal for substituting the redundancy memory cell for the memory cell corresponding to said one bit line when the incremented address coincides with the output of the defective address memory circuit;

a D-F/F circuit for holding the output of said coincidence detection circuit;

wherein said serial selector circuit comprises a data register having a plurality of memory stages, a data transfer circuit for connecting said memory cells to said data register, a plurality of read data buses, a column selector circuit for connecting said data register to said read buses, and a shift register having a plurality of outputs for control of said column selector circuit and adapted to be incremented with said initial address; and

a read data bus selector circuit responsive to said incremented initial address for selecting one of said plurality of read data buses, and wherein an output of said read data bus selector circuit is a clock signal of said D-F/F circuit.