Memory device containing a static ram memory that is adapted for executing a self-test, and integrated circuit containing such a device as an embedded static ram memory

• US 5,325,367 A
• Filed: 08/22/1991
• Issued: 06/28/1994
• Est. Priority Date: 07/13/1988
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Jansen, Joris F. P., Thijssen, Aloysius P., Dekker, Robertus W. C., Beenker, Franciscus P. M.
• Primary Examiner(s): Baker, Stephen M.
• Application Number:
  US07/752,166
• Time in Patent Office: 1,041 Days
• Field of Search: 371/21.3, 371/22.3, 371/22.4, 371/22.5, 371/21.1
• US Class Current: 714/718
• CPC Class Codes: G11C 29/20 using counters or linear-feedback shift registers [LFSR]
• CPC Class Codes: G11C 29/40 using compression techniques

Abstract

A memory device that contains a static RAM memory is provided with data input and data output registers, an address register, and a control register for storing various control signals. The RAM has three principal modes:

a. in a normal mode, all registers are accessible externally so that the memory may fulfill its standard function,

b. in a scan-state, all the cited register constitute a synchronous shift register that may be serially written with a test pattern and serially read with a result pattern; in this way the memory may be subjected to a test according to the scan test principle,

c. in a self test state the communication with the outer world is shut off, the address register counts through successive addresses, the memory is cycled through read-modify or read-modify-read operations, and the data read is conversed to a signature pattern for subsequent scan-out. In this way a quasi stand-alone test facility is realized. Various additional features may be implemented.

Claims

1. A memory device comprising:

a) a static RAM-memory;

b) an address register, a data input register, a data output register, and a control register all operatively coupled to the RAM for executing accesses to said memory,

c) said address, data input and control registers having externally accessible functional interconnections for information communication,

d) all said registers comprising respective parts of a serially activatable test scan chain means, and

e) first control means for activating said memory device alternatively in a scan-state, an operational state, and an independent self-test state, wherein;

in a said scan-state, said test scan chain mean is operative as at least one serial shift register;

in said operational state, at least said address register, said data input register, and said control register are operatively coupled to the memory; and

in said self-test state, during a time when there is an absence of any information communication via any information input of the memory device, said address register, said data input register and said control register are operatively coupled to the memory for autonomously generating successive data test patterns and address test patterns during a plurality of distinct cycles through RAM, and for switching between reading and writing; and

said data output register is operative for receiving successive data result patterns and includes conversion means for converting successive data result patterns to a signature pattern;

said address register and data input register being provided with sequencing means for converting an initialization pattern sequentially to a succession of sequel patterns, and wherein said conversion means are operative in synchronism with the generation of said sequel patterns,

said data input register being provided with a preset mechanism for in the latter register producing a partial test pattern that has a maximum number of 1-0 changeovers between successive bit positions, and said sequencing means has second control means for from said partial test pattern generating successive further partial test patterns in a partial sequence, wherein in said sequence each 1-0 changeover between a random pair of bit positions thereof occurs at least once.

2. A memory device as claimed in claim 1, wherein said conversion means has a hold state for holding any signature pattern generated therein.

3. A memory device as claimed in claim 1, wherein said serial test scan chain is adapted for executing a test operation on said control means and said sequencing means.

4. A memory device as claimed in claim 1, wherein third control means are provided for executing a scan test on the memory itself.

5. An integrated circuit containing a memory device according to claim 1, and also a further data processing subsystem that in said operational state is operatively connected to at least either said data input register, or said address register, or a functional data output coupled to said data output register.

6. A memory device as claimed in claim 1, wherein said serial test scan chain is adapted for executing a test operation on said first control means and said sequencing means.

7. A memory device comprising:

a) a static RAM-memory;

b) an address register, a data input register, a data output register, and a control register all operatively coupled to the RAM for executing accesses to said memory,

c) said address, data input and control registers having externally accessible functional interconnections for information communication,

d) all said registers comprising respective parts of a serially activatable test scan chain means, and

e) first control means for activating said memory device alternatively in a scan-state, an operational state, and an independent self-test state, wherein;

in a said scan-state, said test scan chain means is operative as at least one serial shift register;

in said operational state, at least said address register, said data input register, and said control register are operatively coupled to the memory; and

in said self-test state, during a time when there is an absence of any information communication via any information input of the memory device, said address register, said data input register and said control register are operatively coupled to the memory for autonomously generating successive data test patterns and address test patterns during a plurality of distinct cycles through RAM, and for switching between reading and writing; and

said data output register is operative for receiving successive data result patterns and includes conversion means for converting successive data result patterns to a signature pattern;

said address register and data input register being provided with sequencing means for converting an initialization pattern sequentially to a succession of sequel patterns, and wherein said conversion means are operative in synchronism with the generation of said sequel patterns,

said first control means including a finite state machine, for producing a plurality of control signals controlling in said test state said RAM-memory and said address register, the finite state machine comprising means for driving the plurality of control signals in a succession of control states, a successive control state being determined from a preceding control state and an address register state,

said finite state machine including a sequence of states, starting with a write state for all memory locations, followed by a first read-modify sequence for all memory locations in a first address incrementation direction with a first data background, repeating the same with an inverted data background with respect to said first data background, repeating the same in an opposite address incrementation direction with said first and inverted data backgrounds, respectively, next disabling the memory during a waiting time and thereafter executing a second read-modify sequence for all memory locations in predetermined address incrementation sequence, finally disabling the memory again during a time equal to said waiting time and execute a read sequence for all memory locations in a further predetermined address sequence;

said first and second data backgrounds comprise a plural bit-repetition of (0-1) data patterns to a total n n-bits, and in that any state pertaining to such data background is replayed in a state with a projected data background, wherein half of the data bits of any projecting data background are each projected on two bits of the projected data background, until after ² log n replay operations, any pair of data bits has at least once had a (0-1) pattern difference between them.

8. A memory device comprising:

a) a static RAM-memory;

b) an address register, a data input register, a data output register, and a control register all operatively coupled to the RAM for executing accesses to said memory,

c) said address, data input and control registers having externally accessible functional interconnections for information communication,

d) all said registers comprising respective parts of serially activatable test scan chain means, and

e) first control means for activating said memory device alternatively in a scan-state, an operational state, and an independent self-test state, wherein;

in a said scan-state, said test scan chain means is operative as at least one serial shift register;

in said operational state, at least said address register, said data input register, and said control register are operatively coupled to the memory;

in said self-test state, during a time when there is an absence of any information communication via any information input of the memory device, said address register, said data input register and said control register are operatively coupled to the memory for autonomously generating successive data test patterns and address test patterns during a plurality of distinct cycles through RAM, and for switching between reading and writing; and

said data output register is operative for receiving successive data result patterns and includes conversion means for converting successive data result patterns to a signature pattern;

said address register and data input register being provided with sequencing means for converting an initialization pattern sequentially to a succession of sequel patterns, and wherein said conversion means are operative in synchronism with the generation of said sequel patterns;

said data input register being provided with a preset mechanism for in the latter register producing a partial test pattern that has a maximum number of 1-0 changeovers between successive bit positions, and said sequencing means has second control means for from said partial test pattern generating successive further partial test patterns in a partial sequence, wherein in said sequence each 1-0 changeover between a random pair of bit positions thereof occurs at least once; and

wherein said first control means comprises a finite state machine, for producing a plurality of control signals controlling in said test state said RAM-memory and said address register, the finite state machine comprising means for driving the plurality of control signals in a succession of control states, a successive control state being determined from a preceding control state and an address register state.

9. A memory device as claimed in claim 8, wherein said finite state machine comprises a sequence of states, starting with a write state for all memory locations, followed by a first read-modify sequence for all memory locations in a first address incrementation direction with a first data background, repeating the same with an inverted data background with respect to said first data background, repeating the same in an opposite address incrementation direction with said first and inverted data backgrounds, respectively, next disabling the memory during a waiting time and thereafter executing a second read-modify sequence for all memory locations in a predetermined address incrementation sequence, finally disabling the memory again during a time equal to said waiting time and execute a read sequence for all memory locations in a further predetermined address sequence.

10. A memory device as claimed in claim 9, wherein each said first read-modify sequence is completed to a read-modify-read sequence.

11. A memory device as claimed in claim 8, wherein said address register has address traversing means, for traversing all address positions of the memory in a first sequence, the address register also having reverse traversing means, for traversing all the address positions in a second sequence, the second sequence being in reverse order with respect to the first sequence.

12. A memory device as claimed in claim 11, wherein the traversing means are counting means, the first sequence being in order of successive address positions.

13. A memory device as claimed in claim 8, wherein each said data result pattern comprises a plurality of bits, said plurality of bits being coupled in parallel to a linear feedback shift register, which is comprised in said conversion means.

14. A memory device as claimed in claim 11, wherein said linear feedback shift register comprises a number of shift stages, the number of shift stages being larger than a number of bits in said plurality of bits.

15. A memory device comprising:

a) a static RAM-memory;

b) an address register, a data input register, a data output register, and a control register, all operatively coupled to the RAM for executing accesses to said memory,

c) said address, data input and control registers having externally accessible functional interconnections for information communication,

d) all said registers comprising respective parts of a serially activatable test scan chain means,

e) first control means for activating said memory device alternatively in a scan-state, an operational state, and an independent self-test state, wherein;

in a said scan-state, said test scan chain mean is operative as at least one serial shift register;

in said operational state, at least said address register, said data input register, and said control register are operatively coupled to the memory;

in said self-test state, during at time when there is an absence of any information communication via any information input of the memory device, said address register, said data input register and said control register are operatively coupled to the memory for autonomously generating successive data test patterns and address test patterns during a plurality of distinct cycles through RAM, and for switching between reading and writing; and

said data output register is operative for receiving successive data result patterns and includes conversion means for converting successive data result patterns to a signature pattern; and

waiting means for waiting a predetermined period of time longer than a plurality of clock cycles between writing and reading accesses at an address, no writing accesses being executed in said predetermined period.

16. A memory device as claimed in claim 15, wherein the waiting means comprises a wait counter, said wait counter sharing at least a part of the counting means.