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Associative memory

  • US 5,325,501 A
  • Filed: 08/02/1991
  • Issued: 06/28/1994
  • Est. Priority Date: 08/02/1990
  • Status: Expired due to Fees
First Claim
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1. An associative memory having a first control bus arrangement (any-- type, Vr, cpb, set.s, match, r/w.s, r/w.b, r/w.r, Wand.a, Wand.b, Wor, s.a, reset.b, mode.a mode.a*, prech, ba, mode.b, grant.b, prio etc) for external control, a second memory bus arrangement (t1, t2, id, env, v0, v1, v2, v3) for data comprising:

  • several storage cells (1) connected to said memory bus arrangement for storing a composed information, all of said storage cells being simultaneously controllable by said control bus arrangement in accordance with an operation to be performed, means (LAZY,

         8) in each of said storage cells for storing at least one mark, said mark(s) indicating at least select state(s) or non select state(s) for said storage cell,means internal to the associative memory for making search operations through the memory bus among said cells to set at least one mark, andmeans (11) in each storage cell for communicating with said buses and to control said storage cells to take part in an actual logical operation by setting a priority request state for said storage cells when said operation requests selection, said priority request state being based on said mark(s) in said means (8) in each of said storage cells, anda priority decoder (2) to which all said storage cells are coupled which selects one out of several of said storage cells by reading said priority request state from the means (11) setting said priority request state in all storage cells and simultaneously returning an individual signal to each storage cell in the memory indicating said select of non select state(s).

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