Translation lookaside buffer shutdown scheme

• US 5,325,507 A
• Filed: 02/18/1993
• Issued: 06/28/1994
• Est. Priority Date: 05/02/1986
• Status: Expired due to Term

• Current Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Original Assignee: Silicon Graphics Incorporated (Graphics Properties Holdings, Inc.)
• Inventors: Rowen, Christopher, Hansen, Craig C., Freitas, Danny L.
• Primary Examiner(s): Dixon, Joseph L.
• Assistant Examiner(s): WHITFIELD, MICHAEL
• Application Number:
  US08/019,541
• Time in Patent Office: 495 Days
• Field of Search: 395/425, 365/49
• US Class Current: 365/49.17
• CPC Class Codes: G06F 11/004 Error avoidance G06F11/07 and subgroups take precedence
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 12/1045 associated with a data cache

Abstract

An apparatus for temporarily disabling a translation lookaside buffer in a computer system upon the occurrence of certain predefined system conditions. Such conditions may be of a first type which have been predetermined to indicate a greater risk that two or more virtual addresses stored in the TLB will simultaneously match the incoming virtual address, and/or of a second type in which access to the TLB is not needed. An example of the first type is a reference to an unmapped segment of memory. An example of the second type is the processing of a non-memory-access instruction. The apparatus may further include failsafe circuitry to shut down the TLB if at least a given number of matches occur at any time and for any reason, the given number being greater than 1. The apparatus prevents loss of data or damage to the chip where match comparisons are performed in parallel.

Claims

1. A content addressable memory apparatus comprising:

a plurality of tag registers;

a plurality of data registers, each data register having an output enable for enabling contents of the data register onto an output bus;

means for loading information into a first one of the tag registers independently of contents of a second one of the tag registers;

a plurality of comparators, each of the comparators corresponding with a respective one of the tag registers and generating a match signal indicative of whether contents of the respective one of the tag registers matches an incoming tag signal;

first detection means for activating a multiple match signal when at least a given number of the comparators generate match signals indicating contents of respective ones of the tag registers match the incoming tag signal, the given number being greater than one; and

means for coupling each of the match signals to a respective one of the output enables, the means for coupling to all of the output enables being inhibited if the multiple match signal is active.

2. The content addressable memory apparatus according to claim 1, wherein the first detection means operates in an analog fashion, and wherein the given number is at least equal to a number needed to exceed a threshold of electrical noise.

3. The content addressable memory apparatus according to claim 1, further comprising a second detection means for activating a first signal if a first system condition is present, a probability that contents of at least two of the tag registers will match the incoming tag signal having been predetermined to be greater when the first system condition is present than when the first system condition is not present;

the means for coupling to all of the output enables being further inhibited if the first signal is active.

4. The content addressable memory apparatus according to claim 1, further comprising a third detection means for activating a second signal if a second system condition exists, the second system condition existing only when no address translation is required;

the means for coupling to all of the output enables being further inhibited if the second signal is active.

5. The content addressable memory apparatus according to claim 1, further comprising:

a second detection means for activating a first signal if a first system condition is present, a probability that the contents of at least two of the tag registers will match the incoming tag signal having been predetermined to be greater when the first system condition is present than when the first system condition is not present; and

a third detection means for activating a second signal if a second system condition exists, the second system condition existing only when no address translation is required;

the means for coupling to all of the output enables being further inhibited if the first signal is active or the second signal is active.

6. A content addressable memory apparatus comprising:

a plurality of tag registers;

a plurality of data registers, each data register having an output enable for enabling contents of the data register onto an output bus;

means for loading information into a first one of the tag registers independently of contents of a second one of the rag registers;

a plurality of comparators, each of the comparators corresponding with a respective one of the tag registers and generating a match signal indicative of whether contents of the respective one of the tag registers matches an incoming tag signal;

first detection means for activating a multiple match signal when at least a given number of the comparators generate match signals indicating contents of respective ones of the tag registers match the incoming tag signal, the given number being greater than one; and

means for coupling each of the match signals to a respective one of the output enables, the means for coupling to all of the output enables except a preselected one of the output enables being inhibited if the multiple match signal is active.

7. The content addressable memory apparatus according to claim 6, wherein the first detection means operates in an analog fashion, and wherein the given number is at least equal to a number needed to exceed a threshold of electrical noise.

8. The content addressable memory apparatus according to claim 6, further comprising a second detection means for activating a first signal if a first system condition is present, a probability that contents of at least two of the tag registers will match the incoming tag signal having been predetermined to be greater when the first system condition is present than when the system condition is not present;

the means for coupling to all of the output enables except the preselected one of the output enables being further inhibited if the first signal is active.

9. The content addressable memory apparatus according to claim 6, further comprising a third detection means for activating a second signal if a second system condition exists, the second system condition existing only when no address translation is required;

the means for coupling to all of the output enables except the preselected one of the output enables being further inhibited if the second signal is active.

10. The content addressable memory apparatus according to claim 6, further comprising:

a second detection means for activating a first signal if a first system condition is present, a probability that the contents of at least two of the tag registers will match the incoming tag signal having been predetermined to be greater when the first system condition is present than when the first system condition is not present; and

a third detection means for activating a second signal if a second system condition exists, the second system condition existing only when no address translation is required;

the means for coupling to all of the output enables except the preselected one of the output enables being further inhibited if the first signal is active or the second signal is active.