Method of operating a cache memory including determining desirability of cache ahead or cache behind based on a number of available I/O operations

• US 5,325,509 A
• Filed: 06/21/1993
• Issued: 06/28/1994
• Est. Priority Date: 03/05/1991
• Status: Expired due to Fees

• Current Assignee: Zitel Corp.
• Original Assignee: Zitel Corp.
• Inventors: Lautzenheiser, Marvin
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US08/079,966
• Time in Patent Office: 372 Days
• Field of Search: 395/425, 395/275, 364/200 MS File, 364/900 MS File, 365/400
• US Class Current: 711/137
• CPC Class Codes: G06F 11/1435 using file system or storage system metadata
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 2212/2228 Battery-backed RAM
• CPC Class Codes: G06F 2212/312 In storage controller

Abstract

A computer data storage device made up of both solid state storage and rotating magnetic disk storage maintains a fast response time approaching that of a solid state device for many workloads and improves on the response time of a normal magnetic disk for practically all workloads. The high performance is accomplished by a special hardware configuration coupled with unique procedures and algorithms for placing and maintaining data in the most appropriate media based on actual and projected activity. The system management features a completely searchless method (no table searches) for determining the location of data within and between the two devices. Sufficient solid state memory capacity is incorporated to permit retention of useful, active data, as well as to permit prefetching of data into the solid state storage when the probabilities favor such action. Movement of updated data from the solid state storage to the magnetic disk and of prefetched data from the magnetic disk to the solid state storage is done on a timely, but unobtrusive, basis as background tasks of the described device. A direct, private channel between the solid state storage and the magnetic disk prevents the conversations between these two media from conflicting with the transmission of data between the host computer and the described device. A set of microprocessors manages and oversees the data transmission and storage. Data integrity is maintained through a power interruption via a battery assisted, automatic and intelligent shutdown procedure.

Claims

1. A method for operating a cache memory system serving a host computer, said cache memory system including a mass storage device and a cache memory having a plurality of logical blocks, each logical block having a beginning and an end, and each logical block containing one or more sectors, said method comprising the steps of:

providing a first logical block of said cache memory for containing data accessed by said host; and

performing a cache ahead operation comprising the steps of;

determining that there is no second logical block of said cache memory which contains data that is stored at one or more locations within said mass storage device adjacent a first side of data stored in said first logical block of said cache memory, said first side being selected as a first one of the beginning and the end of data stored in said first logical block;

determining a first distance measured in sectors between a first side of the data accessed by said host which is stored within said cache memory and a first side of said first logical block of said cache memory, said first side of said first logical block being selected as one of the beginning and the end of said first logical block;

based on the size of the current host I/O operation, measured in sectors, determining the number of sequential host I/O operations required to transfer to said host computer data located within said cache memory between said data accessed by said host and said first side of said first logical block;

determining if said number of host I/O operations required is less than a first preselected number; and

if said number of host I/O operations required is less than said first preselected number, copying into a second logical block of said cache memory data which is stored at one or more locations within said mass storage device adjacent data corresponding to data stored at said first side of said first logical block of said cache memory.

2. A method as in claim 1 wherein said first distance is a forward distance measured in sectors from the end of said data accessed by said host to the end of said first logical block of said cache memory.

3. A method as in claim 1 wherein said first distance is a backward distance measured in sectors from the beginning of said data accessed by said host to the beginning of said first logical block of said cache memory.

4. A method as in claim 1 wherein said plurality of logical blocks of said cache memory comprise a plurality of logical blocks dynamically assigned to correspond to logical blocks of said mass storage device.

5. A method as in claim 1 wherein said step of copying comprises the steps of:

determining if data to be copied from said mass storage device has already been stored within said cache memory; and

if not, copying said data to be copied from said mass storage device into a second logical block of said cache memory.

6. A method as in claim 1 wherein said step of performing a cache ahead operation is performed at a lower priority than other requests for access to data stored in said mass storage device.

7. A method as in claim 1 wherein said step of copying is performed using a data channel separate from a data path used by a host to access said cache memory system.

8. A method as in claim 1 which further comprises the steps of:

if said number of host I/O operations required is greater than said first preselected number, or if it has been determined that there is a second logical block of said cache memory which contains data that is stored at one or more locations within said mass storage device adjacent the first side of data stored in said first logical block of said cache memory;

determining that there is no third logical block of said cache memory which contains data that is stored at one or more locations within said mass storage device adjacent a second side of data stored in said first logical block of said cache memory, said second side being selected as a second one of the beginning and the end of data stored in said first logical block;

determining a second distance measured in sectors between the first side of the data accessed by said host which is stored within said cache memory and a second side of said first logical block of said cache memory;

based on the size of the current host I/O operation, measured in sectors, determining a second number of sequential host I/O operations required to transfer to said host computer data located within said cache memory between said data accessed by said host and said second side of said first logical block;

determining if said second number of host I/O operations required is less than a second preselected number; and

if said second number of host I/O operations required is less than said second preselected number, copying into a third logical block of said cache memory data which is stored at one or more locations within said mass storage device adjacent data corresponding to data stored at said second side of said first logical block of said cache memory.

9. A method as in claim 8 wherein said steps of performing a cache ahead operation is performed at a lower priority than other requests for access to data stored in said mass storage device.

10. A method as in claim 8 wherein said steps of copying are performed using a data channel separate from a data path used by a host to access said cache memory system.

11. A method as in claim 8 wherein said plurality of logical blocks of said cache memory comprise a plurality of logical blocks dynamically assigned to correspond to logical blocks of said mass storage device.