Wait control device

• US 5,325,521 A
• Filed: 11/01/1993
• Issued: 06/28/1994
• Est. Priority Date: 02/26/1990
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Nakao, Yuichi, Koyama, Kazumi
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): CHUNG, PHUNG M
• Application Number:
  US08/146,473
• Time in Patent Office: 239 Days
• Field of Search: 371/16.1, 371/16.2, 371/16.3, 371/61, 371/62, 364/270.7, 364/270.6, 364/270.4, 364/270, 364/267.9, 395/575, 395/550
• US Class Current: 714/55
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs

Abstract

A wait control device according to the present invention instructs a central processing unit (CPU) to wait for the start of its operation until the device receives a process completion signal from a memory unit or an I/O unit, and comprises setting means for setting the time of said CPU to wait for the start of its operation in the memory unit or the I/O unit accessed by the CPU, judgement means for judging system operation to be time out error when no process completion signal is presented during said time of the CPU, and selector means for selecting whether it passes a signal concerning the judgement of the time out error or successively waits for said processing completion signal.

Claims

1. A wait control device in a computer, said wait control device being coupled to a bus clock signal line said computer including at least a second device said second device being one of a memory device and an I/O unit, said memory device and said I/O unit having addresses which define at least one address space, said wait control device, comprising:

means for instructing a central processing unit to cause the CPU to suspend operation until said device receives a first signal from said second device indicating completion of processing by said second device;

setting means separate from said CPU, in which a length of time during which the central processing unit suspends operation, is preset by hardware, said setting means being coupled to said means for instructing,

judgment means, separate from said CPU, for generating a time out error signal when said first signal is not presented during said length of time, said judgment means being coupled to said setting means; and

selector means, separate from said CPU, for selecting, based on stored information, whether said wait control device should output the time out error signal in order to selectively permit said wait control device to wait for said first signal, said selector means being coupled to said judgment means.

2. A wait control device according to claim 1 wherein the wait control device includes a timing generator which outputs a wait signal, said timing generator including a counter circuit for counting a bus clock signal received from said bus clock signal line and wherein said judgment means comprises a counter register, coupled to said counter circuit, said counter register storing a plurality of bits, including a select bit and wherein said selector means comprises said select bit, and wherein said setting means comprises a first wait number register, said first wait number register storing a first wait number.

3. A wait control device according to claim 2 further comprising an area-specification circuit, comprising means for defining at least a first address range of said address space and an address comparator means, for outputting an address signal when an address accessed by the CPU is one of the addresses in said first address range, said address comparator means being coupled to said mans for defining, a timing selector means for outputting a signal specified by the wait number register during the time the wait signal is outputted from the timing generator;

and means, coupled to said address comparator means and to said timing selector means, for selectively outputting a first wait controller signal for instructing the CPU to cause the CPU to suspend operation for a length of time depending upon said address space being selected.

4. A wait control device according to claim 3 further comprising a second area-specification circuit said second area-specification circuit including a second wait number registerion for independently setting a second wait number, different from said first wait number, said second area-specification circuit outputting a second wait controller signal and wait controller device also comprising an OR circuit for outputting one of said first wait controller signal and said second wait controller signal.

5. A device as claimed in claim 3, wherein said means for defining further comprises first and second bit registers coupled to said address comparator.

6. A wait control device according to claim 1, wherein the wait control device includes a timing generator which comprises a counter circuit and a counter register, said counter circuit functioning as said instruction means, counting a bus clock signal received from said bus clock signal line during a time period from the reception of a bus start signal to the reception of said first signal and outputting its count value corresponding to a length of time during which said CPU suspends operation of said CPU;

said counter register storing a plurality of bits, coupled to said counter circuit, functioning as set setting means in which a length of time during which said CPU suspends operation set in accordance with said second device, comprising a group of judgment bits as said judgment means for comparing the set value with a count value of said counter circuit and for outputting the time out error signal and a select bit as said selector means;

and said timing generator outputting a timing signal for a count value of said counter circuit.

7. A wait control device in a computer having a memory device and an I/O unit, said wait control device comprising:

means for instructing a central processing unit to suspend operation unit said wait control device receives a signal indicative of completion of processing from one of said memory device and said I/O unit;

setting means located in said one of said memory device and said I/O unit accessed by said central processing unit for setting a length of time during which the central processing unit suspends operation;

judgment means, coupled to said setting means, for generating a time out error signal when said signal indicative of completion of processing is not presented during said length of time;

selector means, coupled to said judgment means, for selecting whether said wait control device should output the time out error signal;

a plurality of area-specification circuits, each coupled to said means for instructing, each of said plurality of area-specification circuits comprising two registers for dividing and specifying an address space and an I/O space in a memory device and an address comparator for comparing the address space specified by the registers with an address from said central processing unit; and

an OR circuit, coupled to each of said plurality of area-specification circuits, for outputting the time out error signal and a signal indicative of one of said plurality of area-specification circuits accessed by said central processing unit.

8. A wait control device in a computer having a plurality of memory devices and a plurality of I/O units, said wait control device comprising:

means for supplying a plurality of lengths of time to a CPU until said wait control device receives a signal indicative or completion of processing from said plurality of memory devices and said plurality of I/O units and for instructing said CPU to suspend operation in accordance with the plurality of lengths of time;

setting means separate from said CPU, coupled to said instruction means, and in which the plurality of lengths of time required for said CPU to suspend operation are set by hardware or other means in accordance with address spaces in said plurality of memory devices and said plurality of I/O units to be accessed by said CPU;

judgment means for generating a time out error signal when no signal indicative of completion of processing is generated within a length of time required for said CPU to suspend operation in accordance with the address spaces in said plurality of memory devices and said plurality of I/O units accessed by said CPU;

selector means, coupled to said judgment means, for selecting whether or not the time out error signal should be effective;

a plurality of area-specification circuits, each coupled to said instruction means, each of said plurality of area-specification circuits comprising;

a wait number register in which a length of time required for said CPU to suspend operation is set in accordance with one of the address spaces in said plurality of memory devices and said plurality of I/O units accessed by said CPU;

two registers for dividing and specifying one address space in said plurality of memory devices and said plurality of I/O units accessed by said CPU;

an address comparator for comparing an address in the address space specified by said registers and an address received from said CPU and for generating an address signal when an address accessed by said CPU is the address in the address space;

a timing selector for receiving the plurality of lengths of time during which said CPU suspends operation received from said instruction means when the time out error signal is not generated and the timing signal thereof and for outputting the length of time set in said wait number register;

a logic circuit for detecting the address signal from said address comparator and the length of time from said timing selector and outputting a wait control signal; and

an OR circuit, coupled to each of said area-specification circuits, for outputting a wait control signal from one of said area-specification circuits accessed by said CPU to said CPU as a data complete signal.