Method for fabricating monolithic chip containing integrated circuitry and suspended microstructure

• US 5,326,726 A
• Filed: 06/21/1993
• Issued: 07/05/1994
• Est. Priority Date: 08/17/1990
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Tsang, Robert W. K., Core, Theresa A.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): TSAI, H JEY
• Application Number:
  US08/080,677
• Time in Patent Office: 379 Days
• Field of Search: 437/228, 437/901, 437/927
• US Class Current: 438/52
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0742 Interleave, i.e. simultaneously forming the micromechanical structure and the CMOS circuit
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 15/125 by capacitive pick-up
• CPC Class Codes: G01P 15/131 with electrostatic counterbalancing means

Abstract

The invention comprises a method for fabricating a monolithic chip containing integrated circuitry as well as a suspended polysilicon microstructure. The inventive method comprises 67 processes which are further broken down into approximately 330 steps. The processes and their arrangement allow for compatible fabrication of transistor circuitry and the suspended polysilicon microstructure on the same chip.

Claims

1. A method of fabricating a microchip which includes a suspended microstructure and circuitry, said method comprising the steps of;

(1) forming transistors in a first region of a surface of a substrate said step including the formation of dielectrics on said substrate,

(2) forming a layer of material on said surface which will act as an etch stop for the etching of oxide,

(3) removing dielectrics formed on said substrate during said formation of said transistors from a second region of said substrate, except for a layer of oxide on said surface, said second region defining where said microstructure will be formed,

(4) passivating said surface in said second region,

(5) depositing a layer of spacer oxide over said surface of said substrate to act as a spacer for the formation of said suspended microstructure,

(6) etching anchor openings in said spacer oxide layer defining anchors from which said suspended microstructure will be supported,

(7) depositing a layer of polysilicon over said spacer oxide form which said suspended microstructure will be formed,

(8) etching said polysilicon to form said polysilicon into said microstructure,

(9) removing said spacer oxide from said first region of said surface,

(10) forming a protective layer of oxide over said polysilicon in said second region,

(11) forming conductive paths on said microchip for electrically interconnecting said transistors to form a circuit and for electrically interconnecting said microstructure to said circuit,

(12) passivating said first region of said microchip, and

(13) etching said spacer oxide layer to remove all of said oxide and release said microstructure into a suspended state.

2. A method as set forth in claim 1 wherein step (1) comprises the step of;

(1.1) implanting dopant into said substrate in said second region so as to improve isolation between different portions of said microstructure.

3. A method as set forth in claim 1 further comprising the step of;

(3.1) implanting dopant into said substrate in said second region to increase the dopant level so as to improve isolation between portions of said microstructure.

4. A method as set forth in claim 1 wherein said layer of material formed in step (2) comprises nitride and further wherein step (12) comprises forming a nitride-to-nitride seal around said first region.

5. A method as set forth in claim 4 wherein step (12) comprises the steps of;

(12.1) depositing a layer of oxide over said nitride layer formed in step (2),

(12.2) selectively etching said oxide deposited in step (12.1) so as to form a channel around said first region, and

(12.3) depositing a second layer of nitride over said microchip so as to form a nitride-to-nitride seal around said first region.

6. A method as set forth in claim 5 wherein step (12) further comprises the step of;

(12.4) removing said nitride layer formed in step (12.3) from said second region.

7. A method as set forth in claim 1 wherein step (11) further includes forming resistors and comprises the steps of;

(11.1) depositing a layer of SiCr on said microchip from which said resistors will be formed,

(11.2) depositing metal on said microchip from which said conductive paths will be formed,

(11.3) selectively etching said metal so as to form said conductive paths, and

(11.4) selectively etching said SiCr so as to form said resistors in a pattern.

8. A method as set forth in claim 7 wherein step (11.2) further comprises the step of;

(11.2.1) sputter coating said microchip with TiW, and

(11.2.2) sputter coating said microchip with AlCu.

9. A method as set forth in claim 8 wherein step (11) further comprises the step of;

(11.5) heating said microchip for a specified interval such that said TiW and said AlCu chemically interact to form an alloy.

10. A method as set forth in claim 1 wherein step (1) comprises the steps of;

(1.2) forming emitters of said transistors while simultaneously forming n+ runners for electrically connecting said microstructure to said circuitry.

11. A method as set forth in claim 1 wherein step (9) comprises selectively etching said spacer oxide.

12. A method as set forth in claim 1 wherein step (6) comprises the steps of;

(6.1) increasing dopant levels in said anchor openings.

13. A method as set forth in claim 1 wherein step (4) comprises the steps of;

(4.1) depositing a layer of oxide over said microchip, and

(4.2) densifying said oxide.

14. A method as set forth in claim 1 wherein step (5) comprises the steps of;

(5.1) depositing said spacer oxide by chemical vapor deposition, and

(5.2) densifying said spacer oxide by exposing it to high temperature.

15. A method as set forth in claim 14 wherein step (5) further comprises the step of;

(5.3) selectively etching divots into a top surface of said spacer layer, whereby, when said microstructure is formed over said spacer layer, bumps are formed on a bottom surface of said microstructure.

16. A method as set forth in claim 1 wherein step (5) further comprises the step of;

(5.3) selectively etching divots into a top surface of said spacer layer, whereby, when said microstructure is formed over said spacer layer, bumps are formed on a bottom surface of said microstructure.

17. A method as set forth in claim 1 wherein step (7) comprises the steps of;

(7.1) depositing said polysilicon over said spacer oxide by low pressure chemical vapor deposition,

(7.2) implanting a dopant into said polysilicon in order to make said polysilicon electrically conductive, and

(7.3) annealing said polysilicon to form said polysilicon.

18. A method as set forth in claim 1 wherein step (10) further comprises etching said spacer oxide from said first region.

19. A method as set forth in claim 1 further comprising the step of;

(10.5) removing from said first region all dielectrics formed in said first region in steps (4) through (10).

20. A method as set forth in claim 11 wherein said method further comprises the step of;

(4.3) depositing a layer of nitride over said microchip, to act as an etch stop for the etching of said spacer oxide in step (9).