DRAM cell utilizing novel capacitor

• US 5,327,375 A
• Filed: 03/02/1993
• Issued: 07/05/1994
• Est. Priority Date: 07/08/1988
• Status: Expired due to Term

• Current Assignee: Eliyahou Harari
• Original Assignee: Eliyahou Harari
• Inventors: Harari, Eliyahou
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US08/024,917
• Time in Patent Office: 490 Days
• Field of Search: 365/149, 365/52, 365/174, 365/182, 365/189.04, 357/23.6, 357/59, 257/309
• US Class Current: 365/149
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/377 having a storage electrode extension located over the transistor

Abstract

A dynamic RAM is provided with enhanced charge storage capacity by increasing the surface area between the two electrodes of the storage capacitor. The first electrode consists of a thick conductive layer whose vertical sidewalls provide the extra surface area for charge storage. The second electrode is used to partially planarize the surface topology. The first electrode can also be used as the gate of a sensing transistor in a signal amplifying cell, as well as in multiport and multistate dynamic RAM cells.

Claims

1. A dynamic RAM cell comprising:

an MOS transfer transistor formed in a semiconductor substrate and having a source region, a drain region, a channel region, and an insulated gate, said transfer transistor being used for selectively writing data into and reading data out of said RAM cells;

a storage capacitor comprising;

a first electrode formed of a first conductive layer, said first electrode being of a granular material and being electrically connected to said source region;

a second conductive electrode overlying said first electrode; and

a storage dielectric insulating layer located between said first and second electrodes;

a bit line connected to said drain; and

a word line connected to said insulated gate,

wherein said first electrode is formed to have an irregular surface formed along the surfaces of the grain boundaries of said first electrode and said storage dielectric and said second conductive electrode substantially follows the contours of said first electrode, thereby increasing the capacitance of said storage capacitor.

2. A cell as in claim 1 wherein said first conductive electrode comprises polycrystalline silicon.

3. A cell as in claim 2 wherein said irregular surface is formed by etching said polycrystalline silicon preferentially along grain boundaries.

4. A cell as in claim 2 wherein said irregular surface is formed by firs growing a relatively thick silicon dioxide on the surface of said polycrystalline silicon and then etching said silicon dioxide.

5. A cell as in claim 4 wherein said storage dielectric insulating layer is formed after said etching of said silicon dioxide.

6. A cell as in claim 1 wherein said storage dielectric insulating layer is sufficiently thin so as to essentially reproduce the surface topology of said irregular surface thereby to substantially increase the capacitance of said storage capacitor.

7. A cell as in claim 1 wherein said storage dielectric insulating layer comprises a layer of silicon dioxide, silicon nitride, a sandwich of silicon dioxide and partially oxidized silicon nitride, or a dielectric material having a dielectric constant higher than the dielectric constant of silicon dioxide.

8. A capacitor as in claim 2 wherein said second electrode comprises a layer of polycrystalline silicon.