Method and apparatus for inhibiting a predecoder when selecting a redundant row line

• US 5,327,380 A
• Filed: 02/08/1991
• Issued: 07/05/1994
• Est. Priority Date: 10/31/1988
• Status: Expired due to Fees

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Norwood, Roger D., Kersh, David V. III
• Primary Examiner(s): Dixon, Joseph L.
• Assistant Examiner(s): WHITFIELD, MICHAEL
• Application Number:
  US07/653,855
• Time in Patent Office: 1,243 Days
• Field of Search: 365/200, 365/230.06, 365/230.03, 365/189.05, 365/195
• US Class Current: 365/195
• CPC Class Codes: G11C 29/787 using a fuse hierarchy

Abstract

A circuit is provided for replacing a defective signal path (94) of a plurality of like signal paths with a redundant signal path (95, 96). A redundant decoder (72) is programmable to respond to a plurality of predetermined addressing signals (RFn) that normally operate to address the defective signal path (94, ROWL1R and ROWLIL). The redundant decoder is operable to generate a disable signal (RREN) in response to the predetermined addressing signals (RFn) and also is operable to select a redundant signal path (95, 96) in response thereto. A decoding circuit (70, 74) normally decodes selected ones of a plurality of addressing signals (RFn) and selects at least one of a plurality of signal paths in response thereto. The decoding circuit (70, 74) is coupled to the redundant decoder (72) for receiving the disable signal (RREN) therefrom. In response to receiving this disable signal (RREN) the decoding circuit (70, 74) will not decode the preselected addressing signals (RFn).

Claims

1. A circuit for replacing a defective signal path with a redundant signal path, comprising:

a global signal source;

a local predecoder coupled to said global signal source and to a plurality of local predecoder lines, said local predecoder liens coupling said predecoder to a plurality of decoders, each of said decoders connected to a respective plurality of word lines, said predecoder and plurality of decoders decoding selected ones of a plurality of addressing signals and selecting at least one of a plurality of signal paths from said global signal source to one of said respective plurality of word lines; and

a redundant decoder connected to a redundant word line and coupled to said predecoder for responding to addressing signals corresponding to a defective signal path, said redundant decoder generating a decoding-inhibiting signal to said predecoder to block said predecoder from selecting one of said at least one of said plurality of signal paths and said redundant decoder selecting a redundant signal path for coupling said global signal source to said redundant word line.

2. The circuit of claim 1, wherein said local predecoder is operable to receive each of a set of said addressing signals corresponding in number to said local predecoder lines, a selected state of one of said set normally operable to enable the establishment of a signal from said global signal source to at least one local predecoder line, said decoding-inhibiting signal operable to block the establishment of the signal path by said selected state.

3. The circuit of claim 1, wherein said redundancy decoder comprises a plurality of addressing transistors, each of said addressing transistors operable by a respective addressing signal to couple a node to a supply of a first voltage, circuitry for establishing a second voltage at said node prior to coupling said node to said supply;

isolation devices for coupling respective ones of each of said addressing transistors to said node, said redundant decoder programmable by selecting ones of said isolation devices to isolate respective transistors from said node such that addressing signals corresponding to said selected ones will be inoperable to couple said node to said supply of the first voltage;

circuitry coupled to said node for generating said decoding-inhibiting signal based on the presence of said second voltage at said node; and

circuitry coupled to said node for establishing a signal path including said redundant signal path based on the presence of said second voltage at said node.

4. The circuit of claim 3, wherein said supply of said first voltage is ground.

5. The circuit of claim 3, wherein said isolation devices each comprise a fuse for coupling a current path of a respective addressing transistor to said node, said redundant decoder programmable by blowing selected ones of said fuses.

6. The circuit of claim 1, wherein said redundant decoder is programmable for responding to either of two different sets of said addressing signals that each correspond to a defective signal path, said redundant decoder operable to select one of up to two redundant signal paths in response thereto.

7. A memory array, comprising:

a global signal source;

a plurality of memory cell arrays arranged in rows and columns, each cell array having a plurality of row liens for accessing respective pluralities of memory cells;

for each cell array, at least one decoding circuit for decoding selected ones of a plurality of addressign signals and selecting at least one of a plurality of signal paths for a global signal from said global signal source to at least one of said row lines in response thereto;

for each decoding circuit, a local predecoder coupled to said global signal source and a plurality of decoders coupled to said local predecoder by a plurality of local predecoder lines, said local predecoder disabled from establishing a signal path from said global signal source to said decoders in response to said local predecoder receiving a disable signal, a redundant decoder programmable for responding to addressing signals corresponding to a defective row line by both generating said disable signal and by coupling said global signal source to a redundant row line; and

said decoding circuit coupled to said redundant decoder for receiving said disable signal therefrom and disabled from decoding said addressing signals in response to receiving said disable signal.

8. The array of claim 7, wherein each said redundant decoder circuit is operable to enable the coupling of said global signal source to one of up to two redundant row lines in the place of up to two defective row lines.

9. The array of claim 7, wherein said cell arrays, said decoding circuits and said redundant decoders are formed within an array area, said global signal source formed exterior of said array area.

10. An array of integrated circuits each requiring the receipt of a global signal for its operation, comprising:

an array area in which said integrated circuits are formed;

a plurality of decoding circuits formed in said array area each for decoding selected ones of a plurality of addressing signals and each operable to select at least one of a plurality of signal paths to respective integrated circuits in response thereto, said decoding circuit including a local predecoder coupled to a global signal source and a plurality of decoders coupled to said predecoder by a plurality of local predecoder liens, said local predecoder disabled form establishing a signal path from said global signal source to said decoders in response to said local predecoder receiving a disable signal;

for each decoding circuit, a redundant decoder formed in said array area and programmable for responding to predetermined ones of said addressing signals by generating said disable signal and by selecting a redundant signal path, at least one redundant integrated circuit coupled to said redundant signal path; and

each said decoding circuit coupled to a respective redundant decoder for receiving said disable signal therefrom, said decoding circuit not decoding said predetermined ones of said addressing signals in response to receiving said disable signal, such that said global signal is routed to said redundant integrated circuit instead of an integrated circuit corresponding to said predetermined ones of said addressing signals.

11. A method for replacing a defective signal path by a redundant signal path, comprising the steps of:

transmitting addressing signals to a redundant decoder and a signal path decoding circuit, said decoding circuit including a local predecoder coupled to a global signal source and a plurality of decoders coupled to said local predecoder by a plurality of predecoder lines;

programming said redundant decoder to transmit a decoding-inhibiting signal to the local predecoder in response to said redundant decoder receiving addressing signals corresponding to a defective signal path;

disabling the local predecoder from establishing a signal path from said global signal source to said plurality of decoders in response to said local predecoder receiving the decoding-inhibiting signal; and

selecting the redundant signal path in response to the redundant decoder receiving said addressing signals corresponding to said defective signal path.

12. The method of claim 11, and further comprising the steps of:

when no defective signal path exists, connecting a node to a supply of a first voltage by selected ones of a plurality of addressing transistors in response to said redundancy decoder receiving addressing signals corresponding to said selected ones of said addressing transistors;

when a defective signal path is discovered, programming the redundant decoder by programming a plurality of isolation devices each associated with a respective addressing signal to isolate a respective addressing transistor from the node;

receiving the addressing signals by the redundant decoder;

blocking by the programmed isolation devices the connection of the supply of the first voltage to the node through addressing transistors corresponding to respective programmed isolation devices; and

generating the disable signal and enabling a global signal to be connected to the redundant signal path both in response to the state of said node being other than the first voltage.

13. The method of claim 12, wherein the isolation devices each comprise a fuse, said step of programming the isolation devices comprising blowing selected ones of said fuses.

14. The method of claim 12, wherein said step of connecting the node to the supply of the first voltage comprises the step of pulling the node to ground.

15. The method of claim 11, and further comprising the step of enabling the connection of one of a plurality of redundant signal paths to a global signal source in replacement of one of a plurality of respective defective signal paths.

16. A method for replacing a defective row line in an array of memory cells arranged in rows and columns, each row of cells coupled to a respective row line, comprising the steps of:

programming a redundant decoder to respond to addressing signals that correspond to the defective row line;

receiving the addressing signals by the redundant decoder and signal path decoding circuit coupled to the row lines;

transmitting a disable signal from the redundant decoder to the decoding circuit in response to receiving the addressing signals corresponding to the defective row line, said decoding circuit including a local predecoder coupled to a global signal source and a plurality of decoders coupled to local predecoder lines;

disabling the local predecoder from establishing a signal path from said global signal source to said decoders in response to said local predecoder receiving the disable signal; and

selecting a redundant row lien in response to the redundant decoder receiving the addressing signals corresponding to the defective row line.

17. The method of claim 16, and further comprising the steps of:

organizing the memory cells into a plurality of arrays on a face of an integrated circuit chip to be disposed in rows and columns;

for each cell array, disposing a decoding circuit and a redundant decoder in proximity thereto;

forming a single global signal generator in a peripheral area of the chip outside of said plurality of arrays; and

coupling the global signal generator to each of the redundant decoders and each of said plurality of arrays the decoding circuits in the array.