Method for building multi-bit parallel Batcher/banyan networks

• US 5,327,420 A
• Filed: 05/20/1992
• Issued: 07/05/1994
• Est. Priority Date: 05/20/1992
• Status: Expired due to Term

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Lyles, Joseph B.
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US07/887,163
• Time in Patent Office: 776 Days
• Field of Search: 370/53, 370/54, 370/58.1, 370/60, 370/94.1, 379/268, 379/271, 379/272
• US Class Current: 370/397
• CPC Class Codes: H04L 49/106 using space switching, e.g. crossbar or matrix
• CPC Class Codes: H04L 49/1507 Distribute and route fabrics, e.g. sorting-routing or Batcher-Banyan
• CPC Class Codes: H04L 49/1553 Interconnection of ATM switching modules, e.g. ATM switching fabrics
• CPC Class Codes: H04L 49/1561 Distribute and route fabrics, e.g. Batcher-Banyan
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3081 ATM peripheral units, e.g. policing, insertion or extraction
• CPC Class Codes: H04L 49/508 Head of Line Blocking Avoidance

Abstract

A switch having a non-blocking, self-routing switching fabric for routing packets from the input ports to the output ports of the switching fabric in accordance with a virtual circuit designation and an output port address that is carried by each packet requires that the output port address for each of the packets being specified by the first few bits of a switch header that is appended to said packet. The switching fabric advantageously is composed of a plurality of parallel connected single bit wide sorting networks followed by a plurality of parallel connected routing networks for providing multi-bit wide data paths between its input ports and its output ports. Moreover, the switching fabric is constructed to have one multi-bit wide sorting network and a plurality of multi-bit wide routing networks for giving plural input ports simultaneous access to identical output ports. For that reason, the address bits for each of the packets are transmitted in bit parallel on all bits of said multi-bit wide data path, together with a prepended stopper ID that distinquishes each packet from any other packet that can be simultaneously routed to the same output port of said switching fabric, thereby preventing packets from different inputs from being intermingled at said output ports.

Claims

1. In a switch having a non-blocking, self-routing switching fabric for routing packets from a plurality of input ports to a plurality of output ports in accordance with a virtual circuit designation and an output port address that is carried by each packet, with said output port address for any given packet being specified by the first few bits of a switch header that is appended to said packet;

said switching fabric being composed of a plurality of parallel connected single bit wide sorting networks that are coupled to a plurality of parallel connected routing networks for providing multi-bit wide data paths between said input ports and said output ports, with each of said sorting networks begin coupled to a plurality of said routing networks for giving plural input ports simultaneous access to each of said output ports;

the address bits for each of said packets being transmitted in bit parallel on all bits of said multi-bit wide data path, together with a prepended stopper ID that distinguishes said packet from any other packet that is simultaneously routed to the same output port of said switching fabric, thereby preventing packets from different sources from being intermingled at said output ports.

2. The switch of claim 1 wherein,

each of said sorting networks is a Batcher sorting network, and

each of said routing networks in a banyan sorting network.