Circuit arrangement for bit rate adaptation

• US 5,327,430 A
• Filed: 12/18/1992
• Issued: 07/05/1994
• Est. Priority Date: 12/23/1989
• Status: Expired due to Term

• Current Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Urbansky, Ralph
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Jung, Min
• Application Number:
  US07/993,259
• Time in Patent Office: 564 Days
• Field of Search: 370/84, 370/102, 370/105.3, 370/108, 375/118, 369/60, 307/475, 331/1 A, 328/155, 328/133, 377/39
• US Class Current: 370/465
• CPC Class Codes: H04J 3/076 Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking
• CPC Class Codes: Y10S 370/914 Rate converter

Abstract

A circuit arrangement for adapting the bit rates of two signals to each other comprises an elastic store (6). The useful data of a first frame-structured signal are written into this store (6) by means of a write address counter (7) and read out again by means of a read address counter (8). A phase comparator (16) is used for comparing the counts of these counters (7, 8). In order to largely avoid jitter in the signal that has been read, the read address counter (8) and the phase comparator (16) are incorporated in a control circuit that controls the clock for the read address counter (8). In this control circuit the output signal of the phase comparator (16) is the control error. The controlled system (17) of the control circuit consists of a controllable oscillator circuit with whose output signal and read address counter (8) is clocked. In order to avoid stationary phase shifts with a constant frequency shift, a controller (18) having a PI behavior (PI=proportionality and integration) is used.

Claims

1. A circuit arrangement for converting the bit rate of a frame structured input signal to a predetermined nominal bit rate, each frame of said input signal including data bits and auxiliary bits;

said circuit arrangement comprising;

an elastic store for receiving and storing data bits of the input signal;

a write address counter for writing data bits of said input signal into said elastic store at the bit rate of said signal, keeping count of the data bits written therein;

a read address counter for reading-out the stored data bits and keeping count thereof, read-out being at a bit rate in accordance with a read clock supplied to said read address counter;

a phase comparator for determining the distance between the counts of said write address counter and said read address counter, and producing a control error signal corresponding to such distance;

a control circuit responsive to said control error signal to produce a frequency control signal;

a transformation circuit for transforming the frequency control signal into a pulse sequence with variable frequency; and

a read clock generating circuit for supplying said read clock to said read address counter substantially at said predetermined nominal bit rate, said read-clock generating circuit comprising an oscillator for receiving said pulse sequence and being controlled thereby to vary the bit rate of the read clock relative to said predetermined nominal bit rate in accordance with said pulse sequence; and

said phase comparator, control circuit, read clock generating circuit and write address circuit constituting a control loop whereby the bit rate of the read clock is controlled so as to rapidly restore the distance between the counts of said write address counter and said read address counter to a desired value in the event of abrupt departures from such desired value due to abrupt changes in the bit rate of said input signal.

2. The circuit of claim 1 wherein the transformation circuit comprises an accumulator for periodically adding the frequency control signal to the content of the accumulator and wherein the pulse sequence comprises pulses generated by the accumulator during overflow.

3. The circuit of claim 1, wherein the read clock generating circuit comprises a phase-locked loop.