High speed CMOS current switching circuit

• US 5,329,192 A
• Filed: 02/25/1993
• Issued: 07/12/1994
• Est. Priority Date: 01/17/1991
• Status: Expired due to Fees

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Wu, Tien-Yu, Hwung, Yung-Peng
• Primary Examiner(s): Kuntz, Curtis
• Assistant Examiner(s): TRAN, SINH N
• Application Number:
  US08/023,169
• Time in Patent Office: 502 Days
• Field of Search: 307/576, 307/350, 307/351, 307/352, 307/353, 307/354, 307/355
• US Class Current: 327/387
• CPC Class Codes: H03K 17/04106 in field-effect transistor switches H03K17/0412, H03K17/0416 take precedence

Abstract

A CMOS current steering switch, especially well-suited for use in high speed switching circuits, has a differential switch transistor pair connected to a node, to which a current source is also connected. The gates of the switch transistor pair are controlled by a pair of buffers. The buffers are designed to avoid both switch transistors being off at the same time by decreasing the switching response time on one transistor of the signal compared to the opposite transistor.

Claims

1. A switching circuit for receiving differential input signals and transmitting output signals to respective output terminals in response thereto comprising:

current steering switch means comprising two MOS transistors, each having a source terminal, the source terminals of both said transistors being connected to define a current input node, a drain terminal, each drain terminal of said transistors being connected to a respective one of said output terminals, and a gate terminal;

current source means connected to said current input node;

means defining a power supply node for connection to a power supply and a ground node corresponding to circuit ground;

a pair of buffer means for generating control signals, each of said control signals is being conveyed to respective one of said gate terminals of said MOS transistors for controlling said respective one of said MOS transistors, each buffer means including a pull-up MOS transistor having a drain terminal connected to said power supply node and a source terminal, and a pull-down MOS transistor having a source terminal connected to said ground node and a drain terminal directly connected to the source terminal of said pull-up MOS transistor, the pull-up and pull-down transistors being of the same conductivity type, each of the differential input signals being coupled to and controlling the gate of the pull-up MOS transistor of one said buffer means and the gate of the pull-down MOS transistor of the other of said buffer means, the control signals generated by said buffer means having a fast fall time and slow rise time.

2. A switching circuit for receiving differential input signals and transmitting output signals to respective output terminals in response thereto comprising:

current steering switch means comprising two MOS transistors, each having a source terminal, the source terminals of both said transistors being connected to define a current input node, a drain terminal, the drain terminals of said transistors each being connected to a respective one of said output terminal, and a gate terminal;

current means connected to said current input node;

means defining a power supply node for connection to a power supply, and a ground node corresponding to circuit ground;

a pair of buffer means for generating control signals each of said control signals is being conveyed to respective one of said gate terminals of said MOS transistors for controlling said respective one of said MOS transistors, each buffer means including a pull-up MOS transistor of a first conductivity type having a drain terminal connected to said power supply node and a source terminals, and a pull-down MOS transistor of a conductivity type opposite to the pull-up transistor having a source terminal connected to ground node and a drain terminal directly connected to the source terminal of said pull-up MOS transistor, each of the differential input signals being coupled to controlling the gate terminals of both the pull-up MOS transistor and the pull-down MOS transistor in each of said buffer means, the control signals generated by said buffer means having a fast fall time and slow rise time.