Multiple biasing phase-lock-loops controlling center frequency of phase-lock-loop clock recovery circuit
First Claim
1. A recovered clock circuit for generating a recovered clock signal having a plurality of selectable center frequencies, the recovered clock circuit being connectable with a digital signal processor (DSP) to form a phase-lock-loop (PLL), the DSP generating a digital error word in response to a phase difference between the recovered clock signal and timing data extracted by the DSP from an input data signal, the recovered clock circuit comprising:
- first biasing PLL means for generating a first biasing signal having a magnitude that is a function of the frequency of a first clock signal;
second biasing PLL means for generating a second biasing signal having a magnitude that is a function of the frequency of a second clock signal;
multiplexor means for passing either the first biasing signal or the second biasing signal as a selected bias signal in response to a select signal;
primary controlled oscillator means for generating the recovered clock signal in response to a phase error signal, the center frequency of the recovered clock signal being a function of the magnitude of the phase error signal; and
multiplying digital-to-analog converter means for generating the phase error signal by modifying the selected bias signal with the digital error word;
whereby the center frequency of the recovered clock signal is principally determined by the selected bias signal, andwhereby the phase of the recovered clock signal is adjusted so as to reduce any phase difference between the recovered clock signal and the timing data.
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Accused Products
Abstract
A recovered clock signal is phase aligned with timing data that has been extracted by a digital signal processor (DSP) from an input signal by a multiple phase-lock-loop (PLL) clock recovery circuit that utilizes a digital error word generated by the DSP. The multiple PLL clock recovery circuit uses a first PLL and a second PLL to generate a first biasing signal and a second biasing signal, respectively, which have a magnitude which is a function of the frequency of a first clock signal and a second clock signal, respectively. A multiplexor allows either the first biasing signal or the second biasing signal to be selected as a selected bias signal. A controlled oscillator generates the recovered clock signal with a center frequency which is a function of the magnitude of a phase error signal. A digital-to-analog converter (DAC) generates the phase error signal by modifying the selected bias signal in response to the digital error word. The first biasing signal and the second biasing signal can be switched in and out of the DAC to quickly bias the DAC to drive the controlled oscillator to a specific center frequency.
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Citations
23 Claims
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1. A recovered clock circuit for generating a recovered clock signal having a plurality of selectable center frequencies, the recovered clock circuit being connectable with a digital signal processor (DSP) to form a phase-lock-loop (PLL), the DSP generating a digital error word in response to a phase difference between the recovered clock signal and timing data extracted by the DSP from an input data signal, the recovered clock circuit comprising:
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first biasing PLL means for generating a first biasing signal having a magnitude that is a function of the frequency of a first clock signal; second biasing PLL means for generating a second biasing signal having a magnitude that is a function of the frequency of a second clock signal; multiplexor means for passing either the first biasing signal or the second biasing signal as a selected bias signal in response to a select signal; primary controlled oscillator means for generating the recovered clock signal in response to a phase error signal, the center frequency of the recovered clock signal being a function of the magnitude of the phase error signal; and multiplying digital-to-analog converter means for generating the phase error signal by modifying the selected bias signal with the digital error word; whereby the center frequency of the recovered clock signal is principally determined by the selected bias signal, and whereby the phase of the recovered clock signal is adjusted so as to reduce any phase difference between the recovered clock signal and the timing data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for generating a recovered clock signal having a plurality of selectable center frequencies that are phase aligned with timing data that has been extracted by a digital signal processor from an input data signal, the method comprising the steps of:
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generating a first biasing signal having a magnitude that is a function of the frequency of a first clock signal; generating a second biasing signal having a magnitude that is a function of the frequency of a second clock signal; selecting either the first biasing signal or the second biasing signal as a selected bias signal in response to a select signal; generating the recovered clock signal in response to a phase error signal, the center frequency of the recovered clock signal being a function of the magnitude of the phase error signal; and generating the phase error signal by modifying the selected bias signal with a digital error word generated by the digital signal processor, the digital error word representing a phase difference between the recovered clock signal and the timing data; whereby the center frequency of the recovered clock signal is principally determined by the selected bias signal, and whereby the phase of the recovered clock signal is adjusted so as to reduce any phase difference between the recovered clock signal and the timing data.
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13. A recovered clock circuit for generating a recovered clock signal having a plurality of selectable center frequencies, the recovered clock circuit being connectable with a digital signal processor (DSP) to form a phase-lock-loop (PLL), the DSP generating a digital error word in response to a phase difference between the recovered clock signal and timing data extracted by the DSP from an input data signal, the recovered clock circuit comprising:
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a first biasing PLL that generates a first biasing signal having a magnitude that is a function of the frequency of a first clock signal; a second biasing PLL that generates a second biasing signal having a magnitude that is a function of the second frequency of a second clock signal; a multiplexor that passes either the first biasing signal or the second biasing signal as a selected bias signal in response to a select signal; a primary controlled oscillator that generates the recovered clock signal in response to a DSP generated restart signal and a phase error signal, the center frequency of the recovered clock signal being a function of the magnitude of the phase error signal; and a digital-to-analog converter that generates the phase error signal by modifying the selected bias signal with the digital error word; whereby the center frequency of the recovered clock signal is principally determined by the selected bias signal, and whereby the phase of the recovered clock signal is adjusted so as to reduce any phase difference between the recovered clock signal and the timing data. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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Specification