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Multiple biasing phase-lock-loops controlling center frequency of phase-lock-loop clock recovery circuit

  • US 5,329,251 A
  • Filed: 04/28/1993
  • Issued: 07/12/1994
  • Est. Priority Date: 04/28/1993
  • Status: Expired due to Fees
First Claim
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1. A recovered clock circuit for generating a recovered clock signal having a plurality of selectable center frequencies, the recovered clock circuit being connectable with a digital signal processor (DSP) to form a phase-lock-loop (PLL), the DSP generating a digital error word in response to a phase difference between the recovered clock signal and timing data extracted by the DSP from an input data signal, the recovered clock circuit comprising:

  • first biasing PLL means for generating a first biasing signal having a magnitude that is a function of the frequency of a first clock signal;

    second biasing PLL means for generating a second biasing signal having a magnitude that is a function of the frequency of a second clock signal;

    multiplexor means for passing either the first biasing signal or the second biasing signal as a selected bias signal in response to a select signal;

    primary controlled oscillator means for generating the recovered clock signal in response to a phase error signal, the center frequency of the recovered clock signal being a function of the magnitude of the phase error signal; and

    multiplying digital-to-analog converter means for generating the phase error signal by modifying the selected bias signal with the digital error word;

    whereby the center frequency of the recovered clock signal is principally determined by the selected bias signal, andwhereby the phase of the recovered clock signal is adjusted so as to reduce any phase difference between the recovered clock signal and the timing data.

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