Programmable gate array with improved interconnect structure, input/output structure and configurable logic block

• US 5,329,460 A
• Filed: 02/01/1993
• Issued: 07/12/1994
• Est. Priority Date: 08/15/1989
• Status: Expired due to Fees

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Wright, Michael J., Shen, Ju, Agrawal, Om P.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US08/012,573
• Time in Patent Office: 526 Days
• Field of Search: 364/490, 364/489, 364/488, 364/716, 307/465, 340/825.83
• US Class Current: 326/39
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17744 for input/output signals

Abstract

A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes direct connections for each configurable logic block in the array to eight neighbors, including adjacent configurable logic blocks and next adjacent configurable logic blocks. Also, the interconnect includes uncommitted long lines which are driven by outputs of configurable logic blocks but not committed through the interconnect to inputs of any specific logic block. Rather, the uncommitted long lines are committed to connections to other segments of the interconnect. The interconnect structure also includes staggered switching matrices at the intersections of the horizontal and vertical buses in the interconnect. Repowering buffers that are configurable in both directions are associated with bidirectional lines in the interconnect, and include a bypass path. The interconnect provides for communication of control signals from off the chip, from any configurable logic block in the array, and from the input/output structures in the array to any or all other configurable logic blocks and input/output blocks in the array.

Claims

1. A configurable logic array comprising:

a substrate; and

a plurality of logic areas defined on the substrate, each logic area having a perimeter and programmable logic circuitry positioned within the perimeter for performing logic operations therein in accordance with user-provided configuration data;

an interconnect network defined on the substrate for carrying signals between the logic areas, wherein said interconnect network is configurable in response to user-supplied configuration data;

wherein each logic area is symmetrically divisible into at least first through fourth logic area portions;

wherein each logic area includes four or more input terminals distributively and symmetrically positioned about the perimeter of the logic area for receiving four or more input signals supplied from outside the perimeter and for conducting the four or more externally supplied input signals into the logic area;

wherein the programmable logic circuitry of each logic area includes combinatorial logic means, operatively coupled to the four or more input terminals of the logic area, for producing a plurality of combinatorial logic signals, each combinatorial logic signal being a function of one or more of the externally supplied input signals;

wherein each logic area further includes a plurality of output macrocells, operatively coupled to the corresponding combinatorial logic means of the logic area and positioned for distributively outputting the combinatorial logic signals produced by the corresponding combinatorial logic means out of the logic area from at least two of the four or more area portions of the logic area; and

wherein the interconnect network has nodes symmetrically distributed about each logic area for supplying input signals to corresponding input terminals of the logic area and for receiving the combinatorial logic signals output from the output macrocells of the logic area.

2. A configurable logic array according to claim 1 wherein the plural logic areas are spaced apart from one another and interconnected by the configurable interconnect network.

3. A configurable logic array according to claim 2 wherein the configurable interconnect network includes sets of interconnect buses symmetrically disposed about each logic area in correspondence with the symmetrically distributed input terminals of each logic area, for supplying input signals to the input terminals of the logic areas.

4. A configurable logic array according to claim 3 wherein each of the interconnect buses symmetrically disposed about each logic area includes the same interconnect resources as found in the other interconnect buses symmetrically disposed about the logic area so that balanced signal routing capability is provided at each logic area portion of each logic area.

5. A configurable logic array according to claim 1 wherein the interconnect network includes at least four tri-state lines running adjacent to the at least first through fourth logic area portions of each of the logic areas;

where there are at least four output macrocells in each logic area; and

wherein each of the four macrocells in each logic area includes a tri-state buffer for outputting the combinatorial logic signals produced by the corresponding combinatorial logic means out of the logic area and onto a corresponding tri-state line adjacent to its corresponding logic area portion.

6. A configurable logic array comprising:

a substrate;

a configuration memory defined on the substrate;

a plurality of pads defined on the substrate, the pads being provided for conducting signals flowing between points on the substrate and points off the substrate;

a plurality of logic areas defined on the substrate, each logic area having a perimeter and top, bottom, left and right portions within the perimeter, each logic area further having;

four or more input terminals positioned about its perimeter for distributively supplying four or more input signals received from outside the perimeter into the top, bottom, left and right portions, of the logic area;

a combinatorial logic circuit, positioned within the perimeter and operatively coupled to the four or more input terminals, for producing a plurality of combinatorial logic signals, each combinatorial logic signal being a combinatorial function of one or more of the supplied input signals; and

four output macrocells, operatively coupled to the logic circuit and positioned for distributively outputting the combinatorial logic signals produced by the logic circuit out of the logic area perimeter respectively from the top, bottom, left and right portions of the logic area; and

where said configurable logic array further comprises;

a configurable interconnect network defined on the substrate for carrying signals between the logic areas;

the interconnect network being symmetrically disposed relative to the top, bottom, left and right portions of each logic area logic.