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Programmable gate array with improved interconnect structure, input/output structure and configurable logic block

  • US 5,329,460 A
  • Filed: 02/01/1993
  • Issued: 07/12/1994
  • Est. Priority Date: 08/15/1989
  • Status: Expired due to Fees
First Claim
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1. A configurable logic array comprising:

  • a substrate; and

    a plurality of logic areas defined on the substrate, each logic area having a perimeter and programmable logic circuitry positioned within the perimeter for performing logic operations therein in accordance with user-provided configuration data;

    an interconnect network defined on the substrate for carrying signals between the logic areas, wherein said interconnect network is configurable in response to user-supplied configuration data;

    wherein each logic area is symmetrically divisible into at least first through fourth logic area portions;

    wherein each logic area includes four or more input terminals distributively and symmetrically positioned about the perimeter of the logic area for receiving four or more input signals supplied from outside the perimeter and for conducting the four or more externally supplied input signals into the logic area;

    wherein the programmable logic circuitry of each logic area includes combinatorial logic means, operatively coupled to the four or more input terminals of the logic area, for producing a plurality of combinatorial logic signals, each combinatorial logic signal being a function of one or more of the externally supplied input signals;

    wherein each logic area further includes a plurality of output macrocells, operatively coupled to the corresponding combinatorial logic means of the logic area and positioned for distributively outputting the combinatorial logic signals produced by the corresponding combinatorial logic means out of the logic area from at least two of the four or more area portions of the logic area; and

    wherein the interconnect network has nodes symmetrically distributed about each logic area for supplying input signals to corresponding input terminals of the logic area and for receiving the combinatorial logic signals output from the output macrocells of the logic area.

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