Subscriber line interface circuit for controlling AC and DC output impedance

• US 5,329,585 A
• Filed: 11/30/1992
• Issued: 07/12/1994
• Est. Priority Date: 11/30/1992
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Susak, David M., Takeshian, Tony, Welty, Dennis L.
• Primary Examiner(s): Dwyer, James L.
• Assistant Examiner(s): WEAVER, SCOTT LOUIS
• Application Number:
  US07/983,197
• Time in Patent Office: 589 Days
• Field of Search: 379/399, 379/400, 379/401, 379/402, 379/405, 379/413, 379/404
• US Class Current: 379/399.01
• CPC Class Codes: H04M 19/005 Feeding arrangements without the use of line transformers
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A subscriber line interface circuit (SLIC) sets AC and DC output impedances as seen by first and second transmission signals. The common mode variation and differential variation of the first and second transmission signals is AC-sensed to provide a common mode feedback signal and a differential feedback signal which in turn controls the AC output impedance. The DC component of the first and second transmission signals is blocked allowing downstream amplifiers to operate at reduced power supply potentials. The DC variation of the first and second transmission signals is also sensed for providing a DC feedback signal to control the DC output impedance.

Claims

1. A subscriber line interface circuit (SLIC) having first and second inputs, comprising:

first means coupled to the first and second inputs of the SLIC for receiving first and second transmission signals having AC and DC signal levels, said first means sensing AC common mode variation and AC differential variation of said first and second transmission signals for providing a common mode feedback signal and a differential feedback signal, said first means including,

(a) a first amplifier having first and second inputs and an output, said output being coupled to said first input of said first amplifier, said first amplifier receiving first and second power supply potentials less than said DC signal level on said first transmission signal,

(b) a second amplifier having first and second inputs and an output, said output being coupled to said first input of said second amplifier, said second amplifier receiving said first and second power supply potentials less than said DC signal level on said second transmission signal,

(c) a first resistor and a first capacitor serially coupled between the first input of the SLIC and said second input of said first amplifier,

(d) a second resistor and a second capacitor serially coupled between the first input of the SLIC and said second input of said first amplifier,

(e) a third resistor coupled between said output of said first amplifier and a first node, and

(f) a fourth resistor coupled between said output of said second amplifier and said first node for providing said common mode feedback signal; and

second means coupled to the first and second inputs of the SLIC for providing an AC output impedance, said second means receiving said common mode feedback signal and said differential feedback signal for controlling said AC output impedance.

2. The SLIC of claim 1 wherein said first means further includes:

a third amplifier having first and second inputs and an output, said first input being coupled to said first node, said second input receiving a third power supply potential;

a fifth resistor coupled between said output of said third amplifier and said first input of said third amplifier;

a fourth amplifier having first and second inputs and an output, said first input being coupled to said output of said third amplifier, said second input receiving said third power supply potential, said output providing said common mode feedback signal; and

a sixth resistor coupled between said output of said fourth amplifier and said first input of said fourth amplifier.

3. The SLIC of claim 2 wherein said first means further includes:

a fifth amplifier having first and second inputs and an output, said first input being coupled to said output of said first amplifier, said second input being coupled to said output of said second amplifier;

a seventh resistor coupled between said output of said fifth amplifier and said second input of said fifth amplifier;

a sixth amplifier having first and second inputs and an output, said first input being coupled to said output of said fifth amplifier, said second input receiving said third power supply potential, said output being coupled to said first input of said fourth amplifier; and

an eighth resistor coupled between said output of said sixth amplifier and said first input of said sixth amplifier.

4. The SLIC of claim 3 wherein said second means further includes:

a seventh amplifier having first and second inputs and an output, said first input being coupled to said output of said fourth amplifier, said second input receiving said third power supply potential; and

first current supply means having an input coupled to said output of said seventh amplifier and having an output for providing a current.

5. The SLIC of claim 4 wherein said second means includes:

an eighth amplifier having first and second inputs and an output, said first input being coupled to said output of said first current supply means, said second input receiving a fourth power supply potential;

a ninth resistor coupled between said output of said eighth amplifier and said first input of said eighth amplifier;

a ninth amplifier having first and second inputs and an output, said first input being coupled to said output of said eighth amplifier;

a tenth resistor coupled between said output of said ninth amplifier and said first input of said ninth amplifier;

an eleventh resistor coupled between said output of said ninth amplifier and a second node;

a twelfth resistor coupled between said second node and said second input of said ninth amplifier; and

a thirteenth resistor coupled between said second node and the first input of the SLIC.

6. The SLIC of claim 5 wherein said second means further includes:

a tenth amplifier having first and second inputs and an output, said first input being coupled to said output of said sixth amplifier, said Second input receiving said third power supply potential; and

second current supply means having an input coupled to said output of said tenth amplifier and having an output for providing a current.

7. The SLIC of claim 6 wherein said second means further includes:

an eleventh amplifier having first and second inputs and an output, said first input being coupled to said output of said second current supply means, said second input receiving a fifth power supply potential;

a fourteenth resistor coupled between said output of said eleventh amplifier and said first input of said eleventh amplifier;

a twelfth amplifier having first and second inputs and an output, said first input being coupled to said output of said eleventh amplifier;

a fifteenth resistor coupled between said output of said twelfth amplifier and said first input of said twelfth amplifier;

a sixteenth resistor coupled between said output of said twelfth amplifier and a third node;

a seventeenth resistor coupled between said third node and said second input of said twelfth amplifier;

an eighteenth resistor coupled between said third node and the second input of the SLIC.

8. A subscriber line interface circuit (SLIC) having first and second inputs, comprising:

first means coupled to the first and second inputs of the SLIC for receiving first and second transmission signals having AC and DC signal levels, said first means sensing DC variation of said first and second transmission signals for providing a DC feedback signal, said first means including,

(a) a first amplifier having first and second inputs and an output, said first input of said first amplifier receiving a first power supply potential,

(b) a first resistor coupled between the first input of the SLIC and a first node,

(c) second and third resistors serially coupled between said first node and said second input of said first amplifier, and

(d) a fourth resistor coupled between said output of said first amplifier and said second input of said first amplifier; and

second means coupled to the first and second inputs of the SLIC for providing a DC output impedance in response to said DC feedback signal, said second means including

(e) a second amplifier having first and second inputs and an output,

(f) a fifth resistor coupled between said output of said first amplifier and said first input of said second amplifier,

(g) a sixth resistor coupled between said first input of said second amplifier and said first node,

(h) a seventh resistor coupled between said first node and said output of said second amplifier, and

(i) an eighth resistor coupled between said output of said second amplifier and said second input of said second amplifier.

9. The SLIC of claim 8 wherein said first means further includes:

a third amplifier having first and second inputs and an output, said first input receiving a second power supply potential;

a ninth resistor coupled between the second input of the SLIC and a second node;

tenth and eleventh resistors serially coupled between said second node and said second input of said third amplifier; and

a twelfth resistor coupled between said second input of said third amplifier and said output of said third amplifier.

10. The SLIC of claim 9 wherein said second means further includes:

a fourth amplifier having first and second inputs and an output;

a thirteenth resistor coupled between said output of said third amplifier and said first input of said fourth amplifier;

a fourteenth resistor coupled between said first input of said fourth amplifier and said second node;

a fifteenth resistor coupled between said second node and said output of said fourth amplifier;

a sixteenth resistor coupled between said output of said fourth amplifier and said second input of said fourth amplifier; and

a capacitor coupled between an interconnection of said second and third resistors and an interconnection of said tenth and eleventh resistors.