Graphics processor nonconfined address calculation system

• US 5,329,617 A
• Filed: 11/10/1993
• Issued: 07/12/1994
• Est. Priority Date: 07/23/1989
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Asal, Michael D.
• Primary Examiner(s): Bayerl, Raymond J.
• Application Number:
  US08/150,569
• Time in Patent Office: 244 Days
• Field of Search: 395/166, 395/165, 395/164, 395/400, 345/200, 345/190, 345/203, 345/28
• US Class Current: 345/569
• CPC Class Codes: G09G 5/391 Resolution modifying circuits, e.g. variable screen formats

Abstract

A graphics processing system allows for fuller utilization of memory space by allowing freedom in performing X-Y conversions to linear addressing for graphics display. The system takes advantage of the fact that many display pitch dimensions can be defined in terms of powers of 2, thereby allowing for simple shifts in the binary value followed by an addition of two such shifted numbers. For non-even situations full multiplication by the pitch is available. This operation is controlled by the values in two registers, which values in turn control the actual shifting and multiplication functions.

Claims

1. A video graphics system, comprising:

a display medium having pixel locations arranged in rows with the address location between adjacent rows defined in terms of pitch used for converting X-Y memory addresses consisting of separate X coordinates and Y coordinates into linear physical locations on said display;

a video presentation memory having established locations therein corresponding to each said pixel location;

a register for controlling said conversion, said register including a first section storing a first value and a second section storing a second value; and

circuitry connected to said register for converting pixel display medium address locations from said memory from said X-Y address format used within said memory to said linear addresses based upon said digits in said register, said circuitry

if said first value of said first section of said register has a predetermined value, performing a full multiplication of said Y coordinate and said pitch,

if said first value of said first section of said register does not have said predetermined value and said second value is zero, shifting said Y coordinate by said first value number of places forming a first resultant, and

if said first value of said first section of said register does not have said predetermined value and said second value is not zero, shifting said Y coordinate by said first value number of places forming a first resultant, shifting said Y coordinate by said second value number of places forming a second resultant, and adding said first resultant and said second resultant forming a third resultant.

2. The video graphics system of claim 1, wherein:

said predetermined value is zero.

3. A method of calculating the linear address of a graphical display from presented X-Y binary value coordinates, said display having a number of bits within each pixel in the X direction and a pitch dimension, expressed in binary format, between rows in the Y direction, said method comprising the steps of:

accessing a first register to determine a first value contained therein;

based upon a determined first value different from a designated value, indicating that the pitch is an exact power of two or that the pitch is calculated to be the sum of two powers of two, shifting a presented Y coordinate binary value a number of places dependent upon said first value to obtain a first resultant value;

based upon said shifting of said Y coordinate, accessing a second register to determine a second value contained therein;

based upon a determined positive second value, shifting said presented Y coordinate binary value a number of places dependent upon said second value to obtain a second resultant value;

adding together said first and second resultant values; and

based upon a determined first value equal to said designated value, indicating that the pitch is neither an exact power of two nor the sum of two powers of two, enabling a full multiplication of said presented Y coordinate binary number by said binary pitch dimension to obtain a third resultant value.

4. The method as set forth in claim 3 further including the steps of:

shifting a presented X coordinate binary value a number of places dependent upon the size of each pixel to obtain a fourth resultant value; and

adding together selected combinations of said first, second, third and fourth resultant values to obtain said linear address corresponding to said presented X and Y coordinates.

5. The method of claim 4 wherein one of said selected combinations comprises said first and fourth resultant values.

6. The method of claim 4 wherein one of said selected combinations comprises said third and fourth resultant values.

7. The method of claim 4 wherein one of said selected combinations comprises said second and fourth resultant values.

8. The method of claim 3, wherein:

said designated value is zero.