Method for etching integrated-circuit layers to a fixed depth and corresponding integrated circuit

• US 5,330,617 A
• Filed: 11/15/1991
• Issued: 07/19/1994
• Est. Priority Date: 11/16/1990
• Status: Expired due to Term

• Current Assignee: Fahrenheit Thermoscope LLC (Intellectual Ventures LLC)
• Original Assignee: Orange S.A.
• Inventors: Haond, Michel
• Primary Examiner(s): DANG, THI D
• Application Number:
  US07/792,262
• Time in Patent Office: 977 Days
• Field of Search: 156/652, 156/653, 156/655, 156/657, 156/661.1, 156/662, 156/644, 156/643, 156/646, 156/659.1, 437/228
• US Class Current: 216/13
• CPC Class Codes: H01L 21/0335 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks

Abstract

The invention relates to a method for etching an integrated-circuit layer to a fixed depth. The method consists in depositing onto the layer to be etched a protective layer forming a stop layer and then onto the latter a reference layer made of a material compatible with that of the layer to be etched the thickness of the reference layer being proportional to the depth of the etch to be produced. A mask is applied to the reference layer and the etching of this layer is carried out by chemical attack until encountering the stop layer. After removal of the mask and of the stop layer, in the etching zone, the reference layer and the layer of material to be etched 1 are simultaneously subjected to a chemical attack until encountering the stop layer. An etch having the plane dimensions of the etch of the reference layer and a depth proportional to the thickness of the reference layer is thus created. Application to the etching of integrated-circuit layers or to the creation of inverted-T-shaped elements.

Claims

1. A method for etching a layer of material of an integrated circuit, over a fixed depth, said method consisting of:

a) depositing onto said layer of material designated as the layer to be etched, a protective layer forming a stop layer,

b) depositing onto said stop layer a reference layer made of a material identical to that of the layer to be etched and whose thickness is made substantially equal to the depth of the etch to be produced in said layer to be etched,

c) applying to said reference layer an etch mask having the plane dimensions of the etch to be produced in said layer to be etched,

d) carrying out the etching by chemical attack, dry or wet, of said reference layer by the intermediary of the etch mask until encountering and exposing a portion of the stop layer in a zone for etching the reference layer,

e) removing said mask and said exposed stop layer;

f) simultaneously subjecting the reference layer, remaining stop layer and the layer of material to be etched in the region of said zone liberated by the removal of the exposed stop layer to a chemical attack, dry or wet, until the remaining stop layer underneath said reference layer is exposed, the reference layer and the remaining stop layer forming an auxiliary mask for the layer to be etched so as to create, in the layer to be etched, an etch having the plane dimensions of the etch of the reference layer and a depth substantially proportional to the thickness of this reference layer.

2. The method as claimed in claim 1,

wherein the layer to be etched in constituted by a material included in the group SiO₂, Si₃ N₄, Si.

3. The method as claimed in claim 1,

wherein the thickness dimension of the reference layer is made equal to a value proportional to the dimension, in the same direction, of the etch to be produced, the ratio of proportionality of these dimensions being made equal, for compatible materials constituting said reference layer, and for appropriate etch modes or etchants with respect to the layer of material to be etched and to the reference layer, to the ratio of the corresponding etch rates.

4. The method as claimed in claim 3, wherein, when the layer to be etched and the reference layer are made of identical material, said dimensions are identical, said reference layer and said layer to be etched being subjected, with a view to their etching, to the same etch modes or etchants.

5. The method as claimed in either of claims 3 and 4, wherein the etch modes or etchants are chosen from among the agents SF₆, C₂ F₆, HCl, Cl₂, CHF₃, CF₄, O₂.

6. A method for providing a raised element into a layer of material of an integrated circuit comprising:

a) depositing onto said layer of material designated as the layer to be etched, a protective layer forming a lower stop layer,

b) depositing onto said lower stop layer a lower reference layer made of a material identical to that of the layer to be etched and whose thickness is made substantially equal to the depth of the etch to be produced in said layer to be etched,

c) depositing onto said lower reference layer an upper stop layer,

d) depositing onto said second stop layer an upper reference layer of the same type and same thickness as said lower reference layer,

e) applying to said upper reference layer an etch mask,

f) carrying out etching by chemical attack, dry or wet, of said upper reference layer by the intermediary of the etch mask until the lower reference layer is exposed,

g) removing the etch mask, and

h) simultaneously subjecting the remaining upper reference layer, remaining upper stop layer and the exposed lower reference layer to a chemical attack, dry or wet, until the remaining upper stop layer underneath said upper reference layer is exposed so as to form said raised element from said lower reference layer underneath said remaining upper stop layer.