Method for fabrication of close-tolerance lines and sharp emission tips on a semiconductor wafer

• US 5,330,879 A
• Filed: 07/16/1992
• Issued: 07/19/1994
• Est. Priority Date: 07/16/1992
• Status: Expired

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Dennison, Charles H.
• Primary Examiner(s): Kight, III, John
• Assistant Examiner(s): Johnson, Rachel
• Application Number:
  US07/914,804
• Time in Patent Office: 733 Days
• Field of Search: 430/5, 430/313, 430/314, 430/323, 430/324, 437/228, 437/229, 437/241, 437/243, 437/913
• US Class Current: 430/313
• CPC Class Codes: G03F 7/00 Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor using photoresist structures for special production processes, see the relevant places, e.g. B44C, H01L, e.g. H01L21/00, H05K
• CPC Class Codes: H01J 9/025 of field emission cathodes
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: Y10S 438/947 Subphotolithographic processing

Abstract

A method for fabricating submicron lines over a semiconductor material by creating a narrow hard mask over the material using a narrow void-producing process. The narrow void is thus used as a mask to form lines that are narrower than those that can be produced by current lithography techniques. The method can also be used to create sharp emission tips for field effect display devices.

Claims

1. A method for fabricating close-tolerance submicron lines on a semiconductor wafer having a gate oxide layer over a substrate and a gate polysilicon layer over the gate oxide, comprising the steps of:

a. depositing a first layer on top of the gate polysilicon layer;

b. forming a loose-tolerance trench in the first layer having a width of less than 1 micrometer (μ

m);

c. depositing a non-conformal material to a predetermined thickness of between 0.3 and 0.45 μ

m over the first layer thereby forming a teardrop-shaped void in the trench, said teardrop-shaped void having a narrow, close-tolerance uniform width dimension;

d. chemically, mechanically polishing (CMP) the non-conformal material down to a top surface of the first layer, thereby exposing the void;

e. depositing a conformal mask material over the first layer and void;

f. CMP polishing and removing the conformal mask material down to the first layer, thereby leaving only the narrow void filled with conformal mask material;

g. anisotropically etching by a photolithography process, the first layer and non-conformal material thereby forming the submicron line below the conformal mask material.

2. The method of claim 1 wherein the loose-tolerance trench is between 0.40 μ

m and 0.7 μ

m.

3. The method of claim 1 wherein the first layer is a mask oxide.

4. The method of claim 1 wherein the non-conformal material is selected from the group consisting of silicon oxide and silicon nitride.

5. The method of claim 1 wherein the conformal mask material is polysilicon.

6. The method of claim 2 wherein the width of the submicron line is less than 0.15 μ

m.

7. A method for fabricating close-tolerance, sharp emission tip on a semiconductor wafer having a gate oxide layer over a substrate and a gate polysilicon layer over the gate oxide, comprising the steps of:

a. depositing a first layer on top of the gate polysilicon layer;

b. forming a loose-tolerance trench in the first layer having a diameter of less than 1 micrometer (μ

m);

c. depositing a non-conformal material to a predetermined thickness of between 0.3 and 0.45 μ

m over the first layer thereby forming a teardrop-shaped void in the trench, said teardrop-shaped void having a narrow, close-tolerance, uniform diameter;

d. chemically, mechanically polishing (CMP) the non-conformal material down to a top surface of the first layer, thereby exposing the void;

e. depositing a conformal mask material over the first layer and void;

f. CMP polishing and removing the conformal mask material down to the first layer, thereby leaving only the void filled with conformal mask material;

g. isotropically etching by a photolithography process the first layer and non-conformal material thereby forming the sharp emission tip below the conformal mask material having a lesser diameter than the loose-tolerance well.

8. The method of claim 7 wherein the loose-tolerance well is between 0.40 μ

m and 0.7 μ

m diameter.

9. The method of claim 7 wherein the first layer is a mask oxide.

10. The method of claim 7 wherein the non-conformal material is selected from the group consisting of silicon oxide and silicon nitride.

11. The method of claim 7 wherein the conformal mask material is polysilicon.

12. The method of claim 8 wherein the diameter of the sharp emission tip is less than 0.15 μ

m.

13. A method for fabricating close-tolerance mask on a semiconductor wafer having a gate oxide layer over a substrate and a gate polysilicon layer over the gate oxide, comprising the steps of:

a. depositing a first layer on top of the gate polysilicon layer;

b. forming a loose-tolerance trench in the first layer having a width of less than 1 micrometer (μ

m);

c. depositing a non-conformal material to a predetermined thickness of between 0.3 and 0.45 μ

m over the first layer thereby forming a teardrop-shaped void in the trench, said teardrop-shaped void having a narrow, close-tolerance uniform width dimension;

d. chemically, mechanically polishing (CMP) the non-conformal material down to a top surface of the first layer, thereby exposing the void;

e. depositing a conformal mask material over the first layer and void; and

then

f. CMP polishing and removing the conformal mask material down to the first layer, thereby leaving only the narrow void filled with conformal mask material.

14. The method of claim 13 wherein the loose-tolerance trench is between 0.40 μ

m and 0.7 μ

m.

15. The method of claim 13 wherein the first layer is a mask oxide.

16. The method of claim 13 wherein the non-conformal material is selected from the group consisting of silicon oxide and silicon nitride.

17. The method of claim 13 wherein the conformal mask material is polysilicon.

18. The method of claim 14 wherein the width of the mask is less than 0.15 μ

m.

19. A method for fabricating close-tolerance, circular mask on a semiconductor wafer having a gate oxide layer over a substrate and a gate polysilicon layer over the gate oxide, comprising the steps of:

a. depositing a first layer on top of the gate polysilicon layer;

b. forming a loose-tolerance well in the first layer having a width of less than 1 micrometer (μ

m);

c. depositing a non-conformal material to a predetermined thickness of between 0.3 and 0.45 μ

m over the first layer thereby forming a teardrop-shaped void in the well, said teardrop-shaped void having a narrow, close-tolerance, uniform diameter;

d. chemically, mechanically polishing (CMP) the non-conformal material down to a top surface of the first layer, thereby exposing the void;

e. depositing a conformal mask material over the first layer and void; and

then

f. CMP polishing and removing the conformal mask material down to the first layer, thereby leaving only the void filled with conformal mask material.

20. The method of claim 19 wherein the loose-tolerance well is between 0.40 μ

m and 0.7 μ

m diameter.

21. The method of claim 19 wherein the first layer is a mask oxide.

22. The method of claim 19 wherein the non-conformal material is selected from the group consisting of silicon oxide and silicon nitride.

23. The method of claim 19 wherein the conformal mask material is polysilicon.