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Method for fabrication of close-tolerance lines and sharp emission tips on a semiconductor wafer

  • US 5,330,879 A
  • Filed: 07/16/1992
  • Issued: 07/19/1994
  • Est. Priority Date: 07/16/1992
  • Status: Expired
First Claim
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1. A method for fabricating close-tolerance submicron lines on a semiconductor wafer having a gate oxide layer over a substrate and a gate polysilicon layer over the gate oxide, comprising the steps of:

  • a. depositing a first layer on top of the gate polysilicon layer;

    b. forming a loose-tolerance trench in the first layer having a width of less than 1 micrometer (μ

    m);

    c. depositing a non-conformal material to a predetermined thickness of between 0.3 and 0.45 μ

    m over the first layer thereby forming a teardrop-shaped void in the trench, said teardrop-shaped void having a narrow, close-tolerance uniform width dimension;

    d. chemically, mechanically polishing (CMP) the non-conformal material down to a top surface of the first layer, thereby exposing the void;

    e. depositing a conformal mask material over the first layer and void;

    f. CMP polishing and removing the conformal mask material down to the first layer, thereby leaving only the narrow void filled with conformal mask material;

    g. anisotropically etching by a photolithography process, the first layer and non-conformal material thereby forming the submicron line below the conformal mask material.

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