Gain linearity correction for MOS circuits

• US 5,331,221 A
• Filed: 08/23/1993
• Issued: 07/19/1994
• Est. Priority Date: 02/12/1991
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Ganesan, Apparajan, Ferguson, Paul F. Jr., Robertson, David H.
• Primary Examiner(s): Zazworsky, John
• Application Number:
  US08/110,327
• Time in Patent Office: 330 Days
• Field of Search: 307/308, 307/304, 307/491, 307/493, 307/494, 307/568, 307/296.1, 307/296.4, 307/296.5, 307/296.8, 307/443, 307/307
• US Class Current: 327/362
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/3211 in differential amplifiers
• CPC Class Codes: H03F 3/45076 characterised by the way of implementation of the active amplifying circuit in the differential amplifier

Abstract

Gain linearity problems caused by impact ionization in a active MOS device are avoided by connecting an MOS shield device in series with the active MOS device so that the overall supply voltage is split across two devices, keeping both devices in a region of operation well below where impact ionization becomes a significant problem. The gate of the MOS shield device is maintained at a voltage proportional to its drain voltage, thereby keeping the device in the saturation mode and avoiding an abrupt mode change associated with prior art shield circuits.

Claims

1. A gain correction circuit for an MOS analog circuit having a gain stage comprising an MOS driver means, an MOS current source transistor connected in a series connection with said driver means and means for applying a supply voltage across said series connection, said gain correction circuit comprising:

an MOS shield transistor connected in series between said driver means and said current source transistor so that an output voltage appears across said shield transistor and said current source transistor, said shield transistor having a gate and a drain, and wherein said shield transistor can operate in a saturation operating mode and a linear operating mode; and

means responsive to said output voltage for applying a bias voltage to said shield transistor gate which bias voltage varies with said output voltage in accordance with a predetermined linear relationship;

wherein said applying means comprises means for sensing said output voltage and means responsive to said sensed output voltage;

wherein said sensing means comprises a voltage divider network and means for applying said output voltage to said voltage divider network.

2. A gain correction circuit according to claim 1 wherein said output voltage applying means comprises a voltage follower.

3. A gain correction circuit according to claim 1 wherein said driver means comprises two MOS active transistors connected in series.

4. A gain correction circuit according to claim 3 wherein both of said active transistors are p-channel devices.

5. A gain correction circuit according to claim 1 wherein said shield transistor is an n-channel device.

6. A gain correction circuit according to claim 1 wherein said output voltage is divided equally across said shield transistor and said current source transistor.