Encoder and decoder

• US 5,331,436 A
• Filed: 09/29/1993
• Issued: 07/19/1994
• Est. Priority Date: 01/07/1991
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ida, Takashi, Dachiku, Kenshi
• Primary Examiner(s): BRINICH, STEPHEN M
• Application Number:
  US08/128,144
• Time in Patent Office: 293 Days
• Field of Search: 358/426, 358/433, 358/133, 358/136, 382/43, 382/56
• US Class Current: 358/426.09
• CPC Class Codes: H04N 19/00 Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
• CPC Class Codes: H04N 19/98 Adaptive-dynamic-range coding [ADRC]
• CPC Class Codes: H04N 19/99 involving fractal coding

Abstract

An encoder comprises a memory for storing a to-be-coded original image, outputting a to-be-coded image signal in response to a to-be-coded region designation signal for designating a to-be-coded region used as a to-be-coded block, and outputting a to-be-transformed image signal in response to a to-be-transformed region designation signal for designating a to-be-transformed region; a transforming circuit for subjecting the to-be-transformed image signal to a predetermined transformation in response to a transformation method designation signal, and outputting a transformed image signal; a deciding circuit for deciding an error of the transformed image signal with reference to the to-be-coded image signal, and a control circuit for outputting, as a code, information on at least the to-be-transformed region and the transformation method which reduce the error decided by the deciding circuit to a predetermined value or below.

Claims

1. A decoder comprising:

first memory means for storing a code including such information on at least a to-be-transformed region and a transformation method that an error of a transformed image signal with reference to a to-be-coded image signal has a value less than a predetermined value, and a mean value of the pixels of a to-be-coded region, said transformed image signal being obtained by transforming a to-be-transformed image signal in accordance with a predetermined transformation method;

designation signal outputting means for transforming the code read out from the first memory means to a to-be-transformed region designation signal and a transformation method designation signal, and outputting the transformed signals;

second memory means for storing the to-be-transformed region image signal and outputting the to-be-transformed region image signal within the to-be-transformed region designated by the to-be-transformed region image designation signal;

transforming means for transforming the to-be-transformed region image signal by means of the transformation method designation signal, outputting the transformation image signal, having the transformation image signal stored in said second memory means as the to-be-transformed region image signal, and repeating transformation until the to-be-transformed image signal is converged; and

a circuit for correcting the transformation image signal by the mean value of the to-be-coded region and outputting the corrected transformation image signal as a decoded signal.

2. The decoder according to claim 1, wherein said second memory means is constituted by first and second frame memories for storing the to-be-transformed image signal, said transforming means transforms the to-be-transformed region image signal stored in said first frame memory, the transformation image signal is stored in said second frame memory as the to-be-transformed region image signal, the to-be-transformed region image signal of said second frame memory is then transformed, and the transformation image signal is stored in said first memory as the to-be-transformed image signal, and these operations are repeated.

5. The decoder according to claim 1, wherein said transforming means is constituted by means for transforming the to-be-transformed image signal read out from said second memory means, and storing the transformation signal at an address in said second memory means from which the to-be-transformed image signal has been read out.

3. The decoder according to claim 14, wherein said second memory means is constituted by a frame memory having first and second memory portions, and said transforming means is constituted by means for transforming the to-be-transformed image signals sequentially read out from said first memory portion, writing the transformation image signals in said second memory portion sequentially, transforming the transformation image signals sequentially read out from said second memory portion after the completion of transformation of one frame, and the transformation image signals are sequentially stored in said first memory portion, and these operations are repeated, thereby producing the decoded signal.

4. The decoder according to claim 3, wherein said transforming means includes means for alternately selecting address signals for designating said first and second memory portions.