Running-average/decimation filter for an oversampling A/D converter

• US 5,331,583 A
• Filed: 06/15/1993
• Issued: 07/19/1994
• Est. Priority Date: 06/19/1992
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Kokubo, Masaru, Hara, Hirotaka, Ishihara, Yukihito
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US08/076,855
• Time in Patent Office: 399 Days
• Field of Search: 364/724.01, 364/724.1, 341/166, 341/167, 341/155
• US Class Current: 708/300
• CPC Class Codes: H03H 17/06 Non-recursive filters

Abstract

A filter processing unit 2 receives the output of an oversampling-type analog/digital (A/D) converter circuit 1. Predetermined information is acquired by a compensation circuit 3-1 with predetermined timing from the filter processing unit 2 in the course of processing for producing a filter output for a predetermined integration-phase state and the predetermined information is fed back to the filter processing unit 2 as compensation information representing a difference in magnitude between a filter output with an integration phase lagging behind or leading ahead of the predetermined integration-phase state and a filter output with an unchanged integration phase in order to produce a controllable-phase filter output DMout. The timing for the acquisition of the compensation information by the compensation circuit 3-1 is controlled by a control circuit 7-1.

Claims

1. A running-average filter for producing a filter output by integrating an input digital signal in accordance with an integration phase and computing a running average of said input digital signal, said running-average filter comprising:

a filter processing unit for processing said input digital signal in a predetermined integration-phase state and producing a plurality of processing results;

a compensation circuit for receiving the processing results and computing a difference in magnitude between one of the processing results with an integration phase lagging behind or leading ahead of said predetermined integration-phase state and another of the processing results with an unchanged integration phase; and

an adder for selectively adding said difference to said one of the processing results for producing the filter output in accordance with external phase-change information.

2. A running-average filter for producing a filter output by integrating an input digital signal in accordance with an integration phase and computing a running average of said input digital signal, said running-average filter comprising:

a filter processing unit for processing said input digital signal in a predetermined integration-phase state and producing a plurality of processing results;

a compensation circuit for acquiring, in response to a timing signal, compensation information representing a difference in magnitude between one of the processing results with an integration phase lagging behind or leading ahead of said predetermined integration-phase state and another of the processing results with an unchanged integration phase from a predetermined node of said filter processing unit with predetermined timing and supplying said compensation information to another predetermined node of said filter processing unit; and

a control circuit for receiving external phase-change information indicating a leading-phase state and a lagging-phase state and, in accordance with said leading-phase and lagging-phase states, generating the timing signal for determining said predetermined timing.

3. A running-average filter according to claim 2, wherein said compensation circuit is a latch circuit latching the processing results in accordance with said timing signal.

4. Apparatus, comprising:

an oversampling-type A/D converter circuit for sampling an input analog signal in accordance with a predetermined sampling clock signal and converting said input analog signal into digital data;

a running-average filter for inputting said digital data, a filter processing unit for processing input digital data in a predetermined integration-phase state and producing a plurality of processing results, a compensation circuit for receiving the processing results an computing a difference in magnitude between one of the processing results with an integration phase lagging behind or leading ahead of said predetermined integration-phase state and another of the processing results with an unchanged integration phase, and an adder for selectively adding said difference to said one of the processing results for producing a filter output in accordance with external phase-change information; and

a digital phase locked loop circuit for synchronizing a phase of said sampling clock signal with a phase of the processing results and generating the external phase-change information supplied to said running-average filter based on said processing results produced by said running-average filter.

5. The apparatus according to claim 4, in a subscriber-line transmission apparatus of an integrated service digital network.

6. A filter which receives a plurality of input signals in a serial manner and which provides an output signal in accordance with the plurality of input signals, comprising:

filter processing means for providing a first output and a second output on a first timing and a second timing in accordance with a plurality of first ones and second ones of the input signals respectively, in a serial manner, the second timing being a different timing from the first timing;

compensation means coupled to said filter processing means for providing a difference between the first output and the second output; and

addition means, coupled to said filter processing means and to said compensation means, and for selectively adding the difference from said compensation means to the first output in response to an information.

7. The filter according to claim 6, coupled to an oversampling-type analog-digital converter, wherein the oversampling-type analog-digital converter provides an output of the input signals with a predetermined period.

8. The filter according to claim 7, wherein a time difference between said first timing and said second timing is said predetermined period.

9. The filter according to claim 8, wherein said second timing is one of a timing lagging behind said first timing and a timing leading ahead of said first timing.

10. The filter according to claim 9, further comprising a digital phase locked loop circuit outputting the information;

and wherein said compensation means selectively outputs one of the first output and the second output under control of the digital phase locked loop circuit.

11. The filter according to claim 10, constituting a subscriber-line transmission apparatus including the oversampling-type analog-digital converter that receives input from a telephone line and outputs the input signals.

12. The filter according to claim 11, wherein said compensation means includes a latch circuit.

13. The filter according to claim 6, wherein said second timing is one of a timing lagging behind said first timing and a timing leading ahead of said first timing.

14. The filter according to claim 6, further comprising a digital phase locked loop circuit outputting the information;

and wherein said compensation means selectively outputs one of the first output and the second output under control of the digital phase locked loop circuit.

15. The filter according to claim 6, constituting a subscriber-line transmission apparatus including an oversampling-type analog-digital converter that receives input from a telephone line and outputs the input signals.

16. The filter according to claim 6, wherein said compensation means includes a latch circuit.