Non-volatile semiconductor memory device with erasure control circuit

• US 5,331,592 A
• Filed: 05/17/1993
• Issued: 07/19/1994
• Est. Priority Date: 05/15/1992
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Yamagata, Yasushi
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US08/062,396
• Time in Patent Office: 428 Days
• Field of Search: 365/185, 365/218, 365/189.09, 365/210
• US Class Current: 365/185.3
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
• CPC Class Codes: G11C 16/3477 Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing

Abstract

A non-volatile semiconductor memory device has an erasure control circuit which, during erasure operation, is switched to a source of a memory cell having a floating gate. The erasure control circuit is constituted by a resistor element and a reference transistor having the same structure as that of the memory cell. One end of the resistor element is connected to a node which, during erasure operation, is electrically connected to the source of the memory cell. The reference transistor has a drain connected to the node, a gate connected to a constant-voltage source, and a source grounded. A floating gate/substrate insulating film of the memory cell and a floating gate/substrate insulating film of the reference transistor are formed simultaneously in the same fabrication step so that the thickness of these insulating films are substantially the same. Even when the thickness of the floating gate/substrate insulating film of the memory cell varies due to production variations, it is possible to prevent the occurrence of an over-erase or a deficient erase by making changes accordingly in the erasure voltage, that is, the voltage at the node.

Claims

1. A non-volatile semiconductor memory device having an erasure control circuit which, during erasure operation, is electrically connected through a switching circuit to a source of a memory cell transistor having a floating gate, said erasure control circuit comprising:

a resistor element having one end connected to a power supply terminal and the other end connected to a node which is electrically connected to the source of said memory cell transistor during the erasure operation; and

a reference transistor which has the same structure as that of said memory cell transistor, and in which a drain electrode is connected to said node, a gate electrode is connected to a constant-voltage input terminal and a source electrode is grounded, said reference transistor having a floating gate/substrate insulating film formed simultaneously through a common process for forming a floating gate/substrate insulating film of said memory cell transistor and the floating gate/substrate insulating film of said reference transistor having substantially the same thickness as that of said memory cell transistor.

2. A non-volatile semiconductor memory device according to claim 1, in which said erasure control circuit further comprises a voltage amplifier connected between said node and said switching circuit.

3. A non-volatile semiconductor memory device according to claim 1, in which said reference transistor has a control gate and a floating gate that are short-circuited.