Composite logic circuit

• US 5,332,936 A
• Filed: 04/14/1993
• Issued: 07/26/1994
• Est. Priority Date: 04/14/1992
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Nakao, Tomoaki
• Primary Examiner(s): Hudspeth, David R.
• Application Number:
  US08/045,708
• Time in Patent Office: 468 Days
• Field of Search: 307/443, 307/448, 307/451, 307/475, 307/264
• US Class Current: 326/68
• CPC Class Codes: H03K 3/356017 using additional transistors in the input circuit H03K3/356104, H03K3/3562 take precedence
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

When a transistor 1 is turned off, and transistors 5 and 7 are both turned on, first and second output signals Oa and Ob both attain a first potential GND irrespective of the logic level of a second logic signal Ib and a third logic signal /Ib. When the transistor 1 is turned on and the transistors 5 and 7 are both turned off by the first logic signal Ia, a transistor 4 is turned off and a transistor 6 is turned on, whereby first and second output signals Oa and Ob attain a second potential VEE and the first potential GND, respectively. When the transistor 1 is turned on, and transistors 5 and 7 are turned off, the transistor 4 is turned on and the transistor 6 is turned off, whereby the first and second output signals Oa and Ob attain the first potential GND and the second potential VEE, respectively. Thus a composite logic circuit can be implemented with 7 transistors.

Claims

1. A composite logic circuit comprising:

a first input node to which a first logic signal having a logic level changing between a first potential and a second potential is supplied,

a second input node to which a second logic signal having a logic level changing between said first potential and a third potential is supplied,

a third input node to which a third logic signal which is an inverted signal of said second logic signal is supplied,

a first output node for providing a first output signal representing an NOR of said first and second logic signals,

a second output node for providing a second output signal representing an NOR of said first and third logic signals,

a first power supply node for receiving a potential equal to said first potential,

a second power supply node for receiving a potential equal to said second potential,

first switching means having one end connected to said second power supply node, and opened and closed in response to said first logic signal,

second switching means connected between the other end of said first switching means and said first output node, and opened and closed in response to said second output signal,

third switching means connected between the other end of said first switching means and said second output node, and opened and closed in response to said first output signal,

fourth switching means connected between said first power supply node and said first output node, and opened and closed in response to said second logic signal,

fifth switching means connected between said first power supply node and said first output node, and opened and closed in response to said first logic signal,

sixth switching means connected between said first power supply node and said second output node, and opened and closed in response to said third logic signal, and seventh switching means connected between said first power supply node and said second output node, and opened and closed in response to said first logic signal.

2. A composite logic circuit comprising:

a first input node to which a first logic signal having a logic level changing between a first potential and a second potential is supplied,

a second input node to which a second logic signal having a logic level changing between said first potential and a third potentials, is supplied,

a third input node to which a third logic signal which is an inverted signal of said second logic signal is supplied,

a first output node for providing a first output signal representing an NAND of said first and second logic signals,

a second output node for providing a second output signal representing an NAND of said first and third logic signals,

a first power supply node for receiving a potential equal to said first potential,

a second power supply potential for receiving a potential equal to said second potential,

first switching means having one end connected to said first power supply node, and opened and closed in response to said first logic signal,

second switching means connected between the other end of said first switching means and said first output node, and opened and closed in response to said second logic signal,

third switching means connected between the other end of said first switching means and said second output node, and opened and closed in response to said third logic signal,

fourth switching means connected between said second power supply node and said first output node, and opened and closed in response to said second output signal,

fifth switching means connected between said second power supply node and said second output node, and opened and closed in response to said first output signal,

sixth switching means connected between said second power supply node and said first output node, and opened and closed in response to said first logic signal, and

seventh switching means connected between said second power supply node and said second output node, and opened and closed in response to said first logic signal.

3. A composite logic circuit comprising:

a first input node to which a first logic signal having a logic level changing between a first potential and a second potential is supplied,

a second input node to which a second logic signal having a logic level changing between said first potential and a third potential is supplied,

a third input node to which a third logic signal which is an inverted signal of said second logic signal is supplied,

a first output node for providing a first output signal representing an NOR of said first and second logic signals,

a second output node for providing a second output signal representing an NOR of said first and third logic signals,

first logic means for bringing the respective signal levels of said first and second output signals to said first potential when the potential of said first logic signal is said second potential,

second logic means for bringing the signal level of said first output signal to said second potential and the signal level of said second output signal to said first potential, when the potential of said first logic signal is said first potential, the potential of said second logic signal is said first potential, and the potential of said third logic signal is said third potential, and

third logic means for bringing the signal level of said first output signal to said first potential and the signal level of said second output signal to said second potential, when the potential of said first logic signal is said first potential, the potential of said second logic signal is said third potential, and the potential of said third logic signal is said first potential.

4. A composite logic circuit comprising:

a first input node to which a first logic signal having a logic level changing between a first potential and a second potential is supplied,

a second input node to which a second logic signal having a logic level changing between said first potential and a third potential is supplied,

a third input node to which a third logic signal which is an inverted signal of said second logic signal is supplied,

a first output node for providing a first output signal representing an NAND of said first and second logic signals,

a second output node for providing a second output signal representing an NAND of said first and third logic signals,

first logic means for bringing the respective signal levels of said first and second output signals to said second potential when the potential of said first logic signal is said first potential,

second logic means for bringing the signal level of said first output signal to said second potential and the signal level of said second output signal to said first potential, when the potential of said first logic signal is said second potential, the potential of said second logic signal is said first potential, and the potential of said third logic signal is said third potential, and

third logic means for bridging the signal level of said first output signal to said first potential, and the signal level of said second output signal to said second potential, when the potential of said first logic signal is said second potential, the potential of said second logic signal is said third potential, and the potential of said third logic signal is said first potential.