Parallel MSD arithmetic using an opto-electronic shared content-addressable memory processor

• US 5,333,117 A
• Filed: 10/04/1993
• Issued: 07/26/1994
• Est. Priority Date: 10/04/1993
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Research Institute, Inc. (NEC Corporation)
• Inventors: Ha, Berlin, Li, Yao
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US08/131,146
• Time in Patent Office: 295 Days
• Field of Search: 364/713, 364/746.2, 364/841, 364/845, 359/107, 359/108
• US Class Current: 708/191
• CPC Class Codes: G06E 1/04 for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation

Abstract

An opto-electronic shared content-addressable memory processor is used to perform parallel modified signed-digit (MSD) arithmetic operations. The MSD arithmetic operation (addition or subtraction of two N-bit numbers) is decomposed into a matrix-matrix multiplication followed by a combination of a threshold and logic operations.

Claims

1. An opto-electronic shared content-addressable memory processor comprising:

an input matrix containing optical data associated with MSD numbers to be arithmetically combined;

a MSD S-CAM matrix;

an output matrix containing data corresponding to optical matrix multiplication of said input matrix data and said MSD S-CAM matrix matrices; and

means coupled to said output matrix for converting the data in said output matrix to obtain MSD result of the numbers arithmetically combined.

2. An opto-electronic shared content-addressable memory processor as set forth in claim 1, further comprising illumination means for passing light through said input matrix and said MSD S-CAM matrix to said output matrix.

3. An opto-electronic shared content-addressable memory processor as set forth in claim 2, wherein said illumination means comprises a laser diode.

4. An opto-electronic shared-content-addressable memory processor as set forth in claim 1, further comprising an identity matrix containing only unit values data along said identity matrix main diagonal entries.

5. An opto-electronic shared content-addressable memory processor as set forth in claim 4, further comprising illumination means for passing light through said identity matrix, said input matrix and said MSD S-CAM matrix to said output matrix.

6. An opto-electronic shared content-addressable memory processor as set forth in claim 5, further comprising a first cylindrical lens juxtaposed to a first spherical lens disposed along a path from said identity matrix to said output matrix a distance of one focal length from said identity matrix and one focal length from said input matrix;

a second spherical lens juxtaposed to said input matrix;

a third spherical lens disposed along said path at a distance of one focal length from said input matrix;

said MSD S-CAM matrix juxtaposed to said third spherical lens;

a second cylindrical lens and a fourth spherical lens in juxtaposition disposed along said path at a distance of one focal length from said MSD S-CAM matrix and disposed at a distance of one focal length from said output matrix.

7. An opto-electronic shared content-addressable memory processor as set forth in claim 5, further comprising first spherical lens and a first cylindrical lens in juxtaposition disposed along a path from said identity matrix to said output matrix a distance one focal length from said identity matrix and one focal length from said input matrix;

a second spherical lens disposed along said path a distance of one focal length from said input matrix and one focal length from said MSD S-CAM matrix, a second cylindrical lens and a third spherical lens in juxtaposition disposed along said path a distance of one focal length from said MSD S-CAM matrix and one focal length from said output matrix.

8. An opto-electronic shared content-addressable memory processor as set forth in claim 1, wherein said input matrix comprises a first spatial light modulator and said MSD S-CAM matrix comprises a second spatial light modulator.

9. An opto-electronic shared content-addressable memory processor as set forth in claim 8, further comprising an input laser array, a first cylindrical lens and a first spherical lens in juxtaposition disposed one focal distance from said input laser array;

a first polarizing beam splitter disposed in a path from said first spherical lens and first cylindrical lens and a first spatial light modulator one focal length from said first lenses;

a first quarter-wave plate disposed in a path between said first polarizing beam splitter and said first spatial light modulator;

a second spherical lens disposed one focal length from said first spatial light modulator;

a second polarizing beam splitter disposed in a path between said second spherical lens and said second spatial light modulator disposed one focal length from said second spherical lens;

a second quarter-wave plate disposed in the path between said second polarizing beam splitter and said second spatial light modulator, and a third spherical lens and a second cylindrical lens in juxtaposition disposed one focal length from said spatial light modulator and one focal length from said output matrix.

10. An opto-electronic shared content-addressable memory processor as set forth in claim 1, further comprising an input laser array, a first cylindrical lens and a first spherical lens in juxtaposition disposed one focal distance from said input laser array;

a first polarizing beam splitter disposed in a path from said first spherical lens and said first cylindrical lens to said input matrix comprising a spatial light modulator disposed one focal length from said first lenses;

a first quarter-wave plate disposed in the path between said first polarizing beam splitter and said input matrix;

a second spherical lens disposed one focal length from said input matrix;

a second polarizing beam splitter disposed in a path between said second spherical lens and said S-CAM matrix disposed one focal length from said second spherical lens;

a second quarter-wave plate disposed in the path between said second polarizing beam splitter and said S-CAM matrix; and

a third spherical lens and a second cylindrical lens in juxtaposition disposed along a path from said S-CAM matrix to said output matrix at a distance of one focal length from said S-CAM matrix; and

said output matrix disposed one focal length from said second cylindrical lens and said third spherical lens.

11. An opto-electronic shared content-addressable memory processor as set forth in claim 1, wherein said means coupled to said output matrix comprises threshold means for determining the level of said data in said output matrix and logic means for obtaining said result from said level of said data in said output matrix.

12. A method of performing optical modified signed-digit arithmetic operations of two numbers comprising the steps of:

converting a first number into electrical data in a first register;

converting a second number into electrical data in a second register;

forming an input matrix containing optical data commensurate with said data in said first register and in said second register;

providing a S-CAM matrix containing data commensurate with generating logic values, 1, 0, and -1;

providing an output matrix for containing data commensurate with the optical multiplication of said input matrix and said S-CAM matrix;

and

processing said data in said output matrix for obtaining the result of the arithmetic operation of said first number and said second number.

13. A method of performing optical modified signed-digit arithmetic operations as set forth in claim 12, further comprising providing an identity matrix containing only unit values data along said identity matrix main diagonal entries.

14. A method of performing optical modified signed-digit arithmetic operations as set forth in claim 13, further comprising illuminating a path through said identity matrix said input matrix, and said S-CAM matrix to said output matrix.

15. A method of performing optical modified signed-digit arithmetic operations as set forth in claim 14, wherein said processing said data comprises applying a threshold to each bit of said data to determine the level of said data and performing logic operation on threshold data to obtain said result.