Error detection and recovery in a DMA controller

• US 5,333,274 A
• Filed: 10/15/1991
• Issued: 07/26/1994
• Est. Priority Date: 10/15/1991
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lohman, Terence J., Hofmann, Richard G., Brannon, Sherwood, Amini, Nader, Boury, Bechara F.
• Primary Examiner(s): RICHARDSON, ROBERT
• Application Number:
  US07/778,040
• Time in Patent Office: 1,015 Days
• Field of Search: 395/275, 395/425, 395/575, 395/700, 395/250
• US Class Current: 714/50
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/0763 by bit configuration check, e.g. of formats or tags
• CPC Class Codes: G06F 11/1402 Saving, restoring, recovering or retrying
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A DMA controller with error circuitry which detects DMA error conditions is disclosed. The error circuitry causes the DMA controller to perform completion tasks before terminating a DMA transfer, advantageously providing a DMA controller which may exit gracefully upon detection of an error condition with the potential of error recovery.

Claims

1. In a data processing system--containing a processor (CPU), a memory subsystem, I/O devices, and a bus linking said memory subsystem to said CPU and devices--apparatus responsive to control information supplied by said CPU, and designating one of said devices, for operating transparent to said CPU to control said bus and conduct a series of multiple DMA data transfer operations over said bus between said memory subsystem and said designated one of said devices;

said apparatus comprising

means effective during each DMA data transfer in said series of data transfers for storing information indicating a predetermined prior state of operation of said DMA controller at completion of a prior data transfer in the same series,

an error detection circuit,

said error detection circuit detecting error in individual said data transfer operations in said series of operations, by monitoring signals indicating the progress of the respective operation, and generating an error indication upon detecting a said error,

a direct memory access control circuit,

said direct memory access control circuit directly controlling said DMA data transfer operations,

said direct memory access control circuit being responsive to said error indication for terminating a respective said series of DMA data transfer operations and performing predetermined completion tasks;

said predetermined completion tasks including tasks for presenting a non-maskable interrupt to said CPU requiring said CPU to recognize said information indicating said predetermined prior state, and tasks for placing said bus under exclusive control of said CPU until it has responded to said interrupt and recognized said predetermined prior state;

recognition of said predetermined prior state enabling said CPU to restart said series of DMA data transfer operations where it had been terminated, rather than requiring repetition of the entire series of data transfer operations including operations that had been successfully completed prior to detection of said error.

2. The apparatus of claim 1 further comprising

an arbiter circuit,

said arbiter circuit receiving said error indication and generating a timeout signal in response to said error indication,

said direct memory access control circuit receiving said timeout signal and performing said completion tasks in response to said timeout signal.

3. The apparatus of claim 2 wherein

said arbiter circuit includes a refresh circuit,

said refresh circuit detecting an error condition when said memory subsystem has not been adequately refreshed and generating a refresh error signal upon detecting this error condition,

said arbiter circuit generating said timeout signal in response to said refresh error signal.

4. The apparatus of claim 2 wherein

said arbiter circuit generates a masked arbitration signal that places said bus under exclusive control of said CPU and inhibits use of said bus by devices other than said CPU until a specific action is taken by said CPU to reset said masked arbitration signal, and

said arbiter circuit includes an arbitration state machine,

said arbitration state machine having unmasked and masked arbitration states, in which said arbiter circuit is respectively permitted and not permitted to arbitrate for control of said bus, said arbitration state machine transitioning to said masked arbitration state in response to said masked arbitration signal.

5. The apparatus of claim 1 wherein

said direct memory access control circuit includes a supervisory state machine, and

said supervisory state machine includes an error state,

said supervisory state machine transitioning to said error state in response to said error indication, and operating in that state to cause said direct memory access control circuit to perform said completion tasks.

6. The apparatus of claim 5 wherein

said direct memory access control circuit includes an execution state machine, and

said execution state machine includes a transfer complete state in which said execution state machine indicates conclusion of an invalid data transfer operation,

said execution state machine transitioning to said transfer complete state at the end of any cycle of activity on said bus which coincides with said timeout signal being active,

said transfer complete state causing said supervisory state machine to transition to said error state after a present transfer is complete.

7. The apparatus of claim 1 further comprising

a control backup circuit,

said control backup circuit storing a copy of said control information.

8. An apparatus for allowing direct access to memory in an information handling system comprising

a processor,

a system memory,

an I/O bus

said I/O bus allowing transfer of information between said processor, said system memory and expansion devices,

an error detection circuit,

said error detection circuit monitoring transfers of information on said bus and generating an error indication upon detecting an error in a said transfer, and

a direct memory access control circuit,

said direct memory access control circuit controlling a direct memory access transfer,

said direct memory access control circuit terminating a direct memory transfer operation, in response to receipt of a said error indication from said error detection circuit, and performing predetermined completion tasks prior to terminating said direct memory access transfer operation, said predetermined completion tasks including tasks to interrupt said processor for notifying said processor of a state said direct memory access control circuit was in prior to said error indication, tasks to present an interrupt for communicating said prior state to said CPU, and tasks to place said bus under exclusive control of said CPU until it has responded to said interrupt and recognized said prior state.

9. The apparatus of claim 8 further comprising

an arbiter circuit,

said arbiter circuit receiving said error indication information and generating a timeout signal based upon said error indication information,

said direct memory access control circuit performing said completion tasks in response to said timeout signal.

10. The apparatus of claim 9 wherein

said arbiter circuit includes a refresh circuit,

said refresh circuit detecting an error condition when said system memory has not been adequately refreshed and generating a refresh error signal upon detecting this error condition,

said arbiter circuit generating said timeout signal in response to said refresh error signal.

11. The apparatus of claim 9 wherein

said arbiter circuit generates a masked arbitration signal, and

said arbiter circuit includes an arbitration state machine,

said arbitration state machine having unmasked and masked arbitration states respectively allowing and preventing arbitration for control of said bus, said arbitration state machine transitioning into a masked arbitration state when said masked arbitration signal is active.

12. The apparatus of claim 8 wherein

said direct memory access control circuit includes a supervisory state machine, and

said supervisory state machine includes an error state,

said error state causing said direct memory access control circuit to perform said predetermined completion tasks.

13. The apparatus of claim 12 wherein

said direct memory access control circuit includes an execution state machine, and

said execution state machine includes a transfer complete state,

said execution state machine transitioning to said transfer complete state at the end of any cycle of activity on said bus which coincides with said timeout signal being active,

said transfer complete state causing said supervisory state machine to transition to said error state after a present transfer is complete.

14. The apparatus of claim 8 further comprising

a control backup circuit,

said control backup circuit storing a copy of said control information.

15. In a computer system including a CPU, a memory subsystem, at least one I/O device, at least one DMA controller having direct access to said memory subsystem, and a bus linking said DMA controller and other elements of said system to said memory subsystem--wherein said DMA controller interfaces between said at least one I/O device and said memory subsystem for conducting DMA data transfers transparent to said CPU in response to control information supplied to said DMA controller by said CPU, wherein said DMA controller has plural internal DMA channels for conducting DMA data transfers concurrently relative to plural I/O devices, and wherein said DMA controller includes means for arbitrating for access to said bus when it is ready to conduct portions of said DMA data transfers relative to individual said DMA channels--error detection and recovery apparatus comprising:

means for detecting an error in a DMA data transfer occurring in any one of said DMA channels;

means effective for each state of operation of said DMA controller, relative to each said DMA channel, for storing information indicating a predetermined prior state of operation of said DMA controller relative to the same DMA channel;

said prior state corresponding to a state the controller was in when it completed a data transfer representing a last valid transfer of data prior to detection of said error;

means responsive to detection of said error for presenting an interrupt to communicate said prior state to said CPU;

means cooperative with said interrupt presenting means for rendering said bus accessible only to said CPU until said CPU responds to said interrupt; and

means for enabling said controller to continue conducting DMA transfers relative to DMA channels other than the channel in which said error was detected, after said CPU has responded to said interrupt, but before said CPU has taken any recovery action relative to the operation that was being conducted relative to the channel in which said error was detected.