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System and method for optimally driving a DC motor

  • US 5,334,917 A
  • Filed: 08/28/1992
  • Issued: 08/02/1994
  • Est. Priority Date: 07/12/1990
  • Status: Expired due to Fees
First Claim
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1. A method for driving a DC-motor comprising a permanent magnet rotor, an inverter and a position detection mechanism capable of generating rotation dependent logical position signals, the method comprising the steps of:

  • a) performing optimization based upon the logical position signals from the position detecting mechanism whereby the commutation points derived from said position signals are each individually displaced by a commutation control unit according to a certain scheme;

    b) detecting the input current level when controlling the commutation for minimum power dissipation in the permanent magnet motor to optimize motor performance by reducing motor vibrations, maximizing motor acceleration, and providing efficient operation at given velocity and load;

    c) applying a digital technique to displace the commutation points individually to a given angle based upon the logical signals, the technique comprising the steps of;

    1)supplying the logical position signals to a pulse detector which creates a first LOAD-signal at each transition of said position signal detected, and a second signal POSITION-- RESET from one of said position signals each first and second signals consist of pulses one clock period long;

    2) resetting a time counter for each LOAD-pulse;

    3) storing the encountered value in a time register the time counter value being an integer proportional to the distance between two position signal transitions;

    4) using said value in the calculation of commutation position, relative to position signal transitions;

    5) transferring said value in a time register holding data for a multiplication algorithm;

    6) storing signal constants in an input memory;

    7) carrying out the following multiplication program;

    
    
    space="preserve" listing-type="tabular">______________________________________ POSITION 0;

    SIGNAL.sub.-- REG1 ;

    = TIME.sub.-- REGISTER * SIGNAL.sub.-- CONSTANT.sub.-- 1;

    SIGNAL.sub.-- REG2 ;

    = TIME.sub.-- REGISTER * SIGNAL.sub.-- CONSTANT.sub.-- 2;

    BEMF.sub.-- REG1 ;

    = TIME.sub.-- REGISTER * BEMF.sub.-- CONSTANT.sub.-- 1;

    BEMF.sub.-- REG2 ;

    = TIME.sub.-- REGISTER * BEMF.sub.-- CONSTANT.sub.-- 2;

    OUT.sub.-- PUT.sub.-- MEMORY[0] ;

    = TIME.sub.-- REGISTER ;

    POSITION 1;

    SIGNAL.sub.-- REG3 ;

    = TIME.sub.-- REGISTER * SIGNAL.sub.-- CONSTANT.sub.-- 3;

    SIGNAL.sub.-- REG4 ;

    = TIME.sub.-- REGISTER * SIGNAL.sub.-- CONSTANT.sub.-- 4;

    BEMF.sub.-- REG3 ;

    = TIME.sub.-- REGISTER * BEMF.sub.-- CONSTANT.sub.-- 3;

    BEMF.sub.-- REG4 ;

    = TIME.sub.-- REGISTER * BEMF.sub.-- CONSTANT.sub.-- 4;

    OUT.sub.-- PUT.sub.-- MEMORY[1] ;

    = TIME.sub.-- REGISTER ;

    POSITION 2;

    SIGNAL.sub.-- REG1 ;

    = TIME.sub.-- REGISTER * SIGNAL.sub. -- CONSTANT.sub.-- 5;

    SIGNAL.sub.-- REG2 ;

    = TIME.sub.-- REGISTER * SIGNAL.sub.-- CONSTANT.sub.-- 6;

    BEMF.sub.-- REG1 ;

    = TIME.sub.-- REGISTER * BEMF.sub.-- CONSTANT.sub.-- 5;

    BEMF.sub.-- REG2 ;

    = TIME.sub.-- REGISTER * BEMF.sub.-- CONSTANT.sub.-- 6;

    OUT.sub.-- PUT.sub.-- MEMORY[2] ;

    = TIME.sub.-- REGISTER ;

    POSITION 3;

    SIGNAL.sub.-- REG3 ;

    = TIME.sub.-- REGISTER * SIGNAL.sub.-- CONSTANT.sub.-- 7;

    SIGNAL.sub.-- REG4 ;

    = TIME.sub.-- REGISTER * SIGNAL.sub.-- CONSTANT.sub.-- 8;

    BEMF.sub.-- REG3 ;

    = TIME.sub.-- REGISTER * BEMF.sub.-- CONSTANT.sub.-- 7;

    BEMF.sub.-- REG4 ;

    = TIME.sub.-- REGISTER * BEMF.sub.-- CONSTANT.sub.-- 8;

    OUT.sub.-- PUT.sub.-- MEMORY[3] ;

    = TIME.sub.-- REGISTER ;

    POSITION 4;

    SIGNAL.sub.-- REG1 ;

    = TIME.sub.-- REGISTER * SIGNAL.sub.-- CONSTANT.sub.-- 9;

    SIGNAL.sub.-- REG2 ;

    = TIME.sub.-- REGISTER * SIGNAL.sub. -- CONSTANT.sub.-- 10;

    BEMF.sub.-- REG1 ;

    = TIME.sub.-- REGISTER * BEMF.sub.-- CONSTANT.sub.-- 9;

    BEMF.sub.-- REG2 ;

    = TIME.sub.-- REGISTER * BEMF.sub.-- CONSTANT.sub.-- 10;

    OUT.sub.-- PUT.sub.-- MEMORY[4] ;

    = TIME.sub.-- REGISTER ;

    POSITION 5;

    SIGNAL.sub.-- REG3 ;

    = TIME.sub.-- REGISTER * SIGNAL.sub.-- CONSTANT.sub.-- 11;

    SIGNAL.sub.-- REG4 ;

    = TIME.sub.-- REGISTER * SIGNAL.sub.-- CONSTANT.sub.-- 12;

    BEMF.sub.-- REG3 ;

    = TIME.sub.-- REGISTER * BEMF.sub.-- CONSTANT.sub.-- 11;

    BEMF.sub.-- REG3 ;

    = TIME.sub.-- REGISTER * BEMF.sub.-- CONSTANT.sub.-- 12;

    OUT.sub.-- PUT.sub.-- MEMORY[5] ;

    = TIME.sub.-- REGISTER ______________________________________ 8) loading signal down counters and bemf down counters with an allocated new value when receiving the LOAD-pulse;

    9) counting down said down counters and at zero value a pulse is generated respectively;

    10) said pulse sets or resets signal and bemf flip-flops whereby respective count down value represents the time at which a phase signal transition should occur.

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