Logical comb filter and chroma signal separation circuit

• US 5,335,021 A
• Filed: 12/02/1991
• Issued: 08/02/1994
• Est. Priority Date: 11/30/1990
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Sawada, Akira
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): HSIA, SHERRIE Y
• Application Number:
  US07/801,811
• Time in Patent Office: 974 Days
• Field of Search: 358/31, 358/39, 358/40, 358/37, 358/329
• US Class Current: 348/664
• CPC Class Codes: H04N 9/78 for separating the brightness signal or the chrominance signal from the colour television signal, e.g. using comb filter

Abstract

A logical comb filter comprises a first delay circuit receiving an input composite video signal called a succeeding signal for delaying the received succeeding signal by one scan line period so as to output a main signal composed of the delayed succeeding signal, and a second delay circuit receiving the main signal for delaying the received main signal by one scan line period so as to output a preceding signal composed of the delayed main signal. An addition circuit is connected at its first input to receive the main signal. A selection and control circuit receives the succeeding signal, the main signal and the preceding signal for supplying the succeeding signal to a second input of the addition circuit when the relation of the main signal>(is greater than) the succeeding signal>the the preceding signal or the relation of the preceding signal>the succeeding signal>the main signal is satisfied. When the relation of the main signal>the preceding signal>the succeeding signal or the relation of the succeeding signal>the the preceding signal>the main signal is satisfied, the selection and control circuit supplies the preceding signal to the second input of the addition circuit. When the relation of the preceding signal>the main signal>the succeeding signal or the relation of the succeeding signal>the main signal>the preceding signal is satisfied, the selection and control circuit supplies the main signal to the second input of the addition circuit.

Claims

1. A logical comb filter comprising a first delay circuit receiving an input signal called a succeeding signal for delaying the received succeeding signal by one scan line period so as to output a main signal composed of the delayed succeeding signal, a second delay circuit receiving said main signal for delaying the received main signal by one scan line period so as to output a preceding signal composed of the delayed main signal, an addition circuit having a first input connected to receive said main signal and a second input, and a selection and control circuit receiving said succeeding signal, said main signal and said preceding signal for supplying to said second input of said addition circuit a signal selected in accordance with the following condition:

said succeeding signal is selected when the relation of said main signal is greater than said succeeding signal is greater than said preceding signal or the relation of said preceding signal is greater than said succeeding signal is greater than said main signal is satisfied;

said preceding signal selected when the relation of said main signal is greater than said preceding signal is greater than said succeeding signal or the relation of said succeeding signal is greater than said preceding signal is greater than said main signal is satisfied; and

said main signal is selected when the relation of said preceding signal is greater than said main signal is greater than said succeeding signal or the relation of said succeeding signal is greater than said main signal is greater than said preceding signal is satisfied;

further including a mean value circuit receiving said succeeding signal and said preceding signal so as to output a mean value signal, and wherein said selection and control circuit also receives said mean value signal and outputs said mean value signal to said second input of said addition circuit when the relation of said preceding signal is greater than said main signal is greater than said succeeding signal or the relation of said succeeding signal is greater than said main signal is greater than said preceding signal is satisfied.

2. A chroma signal separation circuit for separating a chroma signal form a composite video signal, comprising:

a first delay circuit receiving an input composite video signal called a succeeding signal for delaying the received succeeding signal by one scan line period so as to output a main signal composed of the delayed succeeding signal;

a second delay circuit receiving said main signal for delaying the received main signal by one scan line period so as to output a preceding signal composed of the delayed main signal;

a first addition circuit receiving said succeeding signal and said main signal for outputting a succeeding difference signal as the result of addition;

a second addition circuit receiving said main signal and said preceding signal for outputting a preceding difference signal as the result of addition;

a first absolute value circuit receiving said succeeding difference signal for outputting a succeeding difference absolute value signal;

a second absolute value circuit receiving said preceding difference signal for outputting a preceding difference absolute value signal;

a first coefficient circuit receiving said succeeding difference absolute value signal for multiplying said succeeding difference absolute value signal by a first coefficient K1 or a second coefficient K2 so as to generate a first multiplication signal;

a second coefficient circuit receiving said preceding difference absolute value signal for multiplying said preceding difference absolute value signal by the first coefficient K1 or the second coefficient K2 so as to generate a second multiplication signal;

a different sign detection circuit receiving said succeeding difference signal and said preceding difference signal for detecting consistency/inconsistency in positive/negative sign between said succeeding difference signal and said preceding difference signal so as to generate a different sign discrimination signal;

a first comparator receiving an output of said first coefficient circuit and said preceding difference absolute value signal for generating a first large/small discrimination signal;

a second comparator receiving an output of said second coefficient circuit and said succeeding difference absolute value signal for generating a second large/small discrimination signal;

a first selection circuit controlled by said different sign discrimination signal for controlling said first and second coefficient circuit so as to designate one of said first and second coefficients K1 and K2 to be multiplied;

a circuit receiving said succeeding signal, said main signal and said preceding signal for generating a preceding comb signal, a succeeding comb signal and a three-line comb signal;

a second selection circuit receiving said three-line comb signal and said preceding comb signal and controlled by said second large/small discrimination signal so as to select one of said three-line comb signal and said preceding comb signal; and

a third selection circuit receiving an output of said second selection circuit and said succeeding comb signal and controlled by said first large/small discrimination signal so as to output a selected one of said output of said third selection circuit and said succeeding comb signal, as a chroma signal.

3. A chroma signal separation circuit for separating a chroma signal from a composite video signal, comprising:

a first delay circuit receiving an input composite video signal called a succeeding signal for delaying the received succeeding signal by one scan line period so as to output a main signal composed of the delayed succeeding signal;

a second delay circuit receiving said main signal for delaying the received main signal by one scan line period so as to output a preceeding signal composed of the delayed main signal;

a first addition circuit receiving said succeeding signal and said main signal for outputting a succeeding difference signal as the result of addition;

a second addition circuit receiving said main signal and said preceding signal for outputting a preceding difference signal as the result of addition;

a first absolute value circuit receiving said succeeding difference signal for outputting a succeeding difference absolute value signal;

a second absolute value circuit receiving said preceding difference signal for outputting a preceding difference absolute value signal;

a different sign detection circuit receiving said succeeding difference signal and said preceding difference signal for detecting consistency/inconsistency in positive/negative sign between said succeeding difference signal and said preceding difference signal so as to generate a different sign discrimination signal;

a first coefficient circuit receiving said preceding difference absolute value signal for outputting an inverted preceding difference absolute value signal;

a third addition circuit receiving said succeeding difference absolute value signal and said inverted preceding difference absolute value signal for outputting an addition signal;

a positive sign detection circuit receiving said addition signal for detecting a positive sign of said addition signal so as to generate a positive sign discrimination signal;

a first selection circuit receiving said succeeding difference absolute value signal and said preceding difference absolute value signal and controlled by said positive sign discrimination signal so as to select one of said succeeding difference absolute value signal and said preceding difference absolute value signal;

a third absolute value circuit receiving said addition signal for outputting an absolute value signal of said addition signal;

a second coefficient circuit receiving an output of said first selection circuit for multiplying said output of said first selection circuit by a first coefficient K1 so as to generate a first multiplication signal;

a third coefficient circuit receiving said absolute value signal of said addition signal for multiplying said absolute value signal of said addition signal by a second coefficient K2 so as to generate a second multiplication signal;

a second selection circuit receiving said first multiplication signal and said output of said first selection circuit and controlled by said different sign discrimination signal so as to select one of said first multiplication signal and said output of said first selection circuit;

a third selection circuit receiving said absolute value signal of said addition signal and said second multiplication signal and controlled by said different sign discrimination signal so as to select one of said absolute value signal of said addition signal and said second multiplication signal;

a comparator receiving an output of said second selection circuit and an output of said third selection circuit for generating a large/small discrimination signal;

a circuit receiving said succeeding signal, said main signal and said preceding signal for generating a preceding comb signal, a succeeding comb signal and a three-line comb signal;

a fourth selection circuit receiving said succeeding comb signal and said preceding comb signal and controlled by said positive sign discrimination signal so as to select one of said succeeding comb signal and said preceding comb signal; and

a fifth selection circuit receiving an output of said fourth selection circuit and said three-line comb signal and controlled by said large/small discrimination signal so as to output a selected one of said output of said fourth selection circuit and said three-line comb signal, as a chroma signal.

4. A logical comb filter comprising

input means for deriving first, second and third signals from an input signal including a first delay circuit receiving an input signal for delaying the received input signal by one scan line period to produce a main signal composed of the delayed input signal, a second delay circuit receiving said main signal for delaying the received main signal by one scan line period to produce a preceding signal composed of the delayed main signal, said first, second and third signals being derived from said input signal, said main signal and said preceding signal,

discrimination means for receiving said first, second and third signals for producing first, second and third discrimination signals,

control signal generating means for generating first and second control signals in response to said first, second and third discrimination signals, and

a selection circuit means for receiving said first, second and third signals and controlled by said first and second control signals for selecting said second signal in response to a first state of said first control signal, and for selecting either said third signal or said first signal in accordance with said second control signal and a second state of said first control signal.

5. A logical comb filter as recited in claim 4, wherein said control signal generating means includes

a first exclusive-OR circuit receiving said first and second discrimination signals and generating said first control signal in response thereto, and

a second exclusive-OR circuit receiving said second and third discrimination signals and generating said second control signal in response thereto, and wherein

said first state of said first control signal indicates coincidence of said first and second discrimination signals and said second state of said first control signal indicate inconsistency of said first and second discrimination signals.

6. A logical comb filter as recited in claim 4, wherein said first, second and third signals are said input signal, said main signal and said preceding signal, respectively.

7. A logical comb filter as recited in claim 4, wherein said discrimination means includes

a first comparison circuit receiving and comparing said second signal and said third signal for generating said first discrimination signal, a second comparison circuit receiving and comparing said second signal and said first signal for generating said second discrimination signal, a third comparison circuit receiving and comparing said third signal and said first signal for generating said third discrimination signal.

9. A logical comb filter as recited in claim 4, further including

an addition circuit receiving an output of said selection circuit means and said second signal for outputting a result of addition as an output signal.

10. A logical comb filter as recited in claim 9, wherein said second signal is said main signal.

8. A logical comb filter comprising a first delay circuit receiving an input signal for delaying the received input signal by one scan line period so as to output a main signal composed of the delayed input signal, a second delay circuit receiving said main signal for delaying the received main signal by one scan line period so as to output a preceding signal composed of the delayed main signal, a first comparison circuit receiving and comparing said main signal and said preceding signal for generating a first large/small discrimination signal, a second comparison circuit receiving and comparing said main signal and said input signal for generating a second large/small discrimination signal, a third comparison circuit receiving and comparing said preceding signal and said input signal for generating a third large/small discrimination signal, a first exclusive-OR circuit receiving said first and second large/small discrimination signals, a second exclusive-OR circuit receiving said second and third large/small discrimination signals, a selection circuit receiving said input signal, said main signal and said preceding signal and controlled by outputs of said first and second exclusive-OR circuits so as to select said main signal when the output of said first exclusive-OR circuit indicates coincidence, and to select either said preceding signal or said input signal in accordance with the output of said second exclusive-OR circuit when the output of said first exclusive-OR circuit indicates inconsistency, and an addition circuit receiving said main signal and an output of said selection circuit for outputting a result of addition as an output signal.

11. A logical comb filter comprising

input means for deriving a main signal and a preceding signal from an input signal including a first delay circuit receiving an input signal for delaying the received input signal by one scan line period to produce said main signal composed of the delayed input signal, a second delay circuit receiving said main signal for delaying the received main signal by one scan line period to produce said preceding signal composed of the delayed main signal,

discrimination means for receiving said input signal, said main signal and said preceding signal for producing first, second and third discrimination signals,

control signal generating means for generating first and second control signals in response to said first, second and third discrimination signals, and

a selection circuit means for receiving said input signal, said main signal and said preceding signal and controlled by said first and second control signals for selecting said main signal in response to a first state of said first control signal, and for selecting either said preceding signal or said input signal in accordance with said second control signal and a second state of said first control signal.