Time base correcting device

• US 5,335,077 A
• Filed: 06/26/1992
• Issued: 08/02/1994
• Est. Priority Date: 07/03/1991
• Status: Expired due to Term

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Ikeda, Shingo, Gohda, Makoto, Yamashita, Shinichi
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): LEE, MICHAEL
• Application Number:
  US07/906,267
• Time in Patent Office: 767 Days
• Field of Search: 358/148, 358/149, 358/158, 358/159, 358/320, 358/326, 358/325, 358/336, 358/337, 358/160, 358/324, 358/19
• US Class Current: 386/202
• CPC Class Codes: H04N 9/896 using a digital memory with independent write-in and read-out clock generators

Abstract

A time base correcting device inputs a video signal including a sync. signal and a burst signal, produces an error signal representing a phase difference between a clock signal synchronized with the sync. signal and the burst signal, writes the video signal into the memory in synchronism with the clock signal having a phase thereof adjusted in accordance with the error signal, produces an interpolation signal to interpolate a plurality of adjacent error signals along a time base and controls the readout from the memory by the error signals and the interpolation signal. In this manner, it attains time base correction, particularly velocity error correction with high accuracy.

Claims

1. A time base correcting device comprising:

(a) input means for inputting a video signal including a sync. signal and a burst signal;

(b) means for generating a first clock signal synchronized with the sync. signal of the video signal inputted by said input means;

(c) phase difference detection means for detecting a phase difference between said burst signal and said first clock signal at a predetermined interval to produce an error signal representing said phase difference;

(d) phase adjustment means for adjusting the phase of said first clock in accordance with said error signal;

(e) a memory for storing the video signal supplied from said input means in synchronism with said first clock supplied through said phase adjustment means;

(f) interpolation means for generating an interpolation signal at said predetermined interval by using a plurality of error signals produced by said phase difference detection means which are successive along a time base; and

(g) readout control means for controlling the readout from said memory by using a difference between said interpolation signal and said error signal.

2. A time base correcting device according to claim 1 wherein said interpolation means include at least one series-connected delay circuit for delaying said error signal by said predetermined interval and an adder for weight-adding the output of said delay circuit to produce the interpolation signal.

3. A time base correcting device according to claim 2 wherein said readout control means includes a pair of subtractors for calculating differences between said interpolation signal from said adder, and two error signals close to said interpolation signals on the time base.

4. A time base correcting device according to claim 3 wherein said readout control means further includes an integrator for sequentially integrating the outputs of said pair of subtractors.

5. A time base correcting device according to claim 1, wherein said interpolation means includes a subtractor for differentiating the error signals adjacent along the time base, at least one series-connected delay circuit for delaying the output of said subtractor by said predetermined interval and an adder for weight-adding the output of said delay circuit to produce differences between the error signals adjacent along the time base and the interpolation signal.

6. A time base correction device according to claim 1 wherein said readout control means includes an integrator for integrating the differences between the error signals adjacent along the time base and the interpolation signal.

7. A time base correcting device according to claim 6 wherein said readout control means further includes reset means for resetting said integrator at said predetermined interval.

8. A time base correcting device according to claim 6 wherein said readout control means further includes a phase adjustment circuit for adjusting a phase of a clock having a predetermined frequency by the output of said integrator to produce a second clock for controlling the readout of said memory.

9. A time base correcting device comprising:

(a) input means for inputting a video signal including a signal of a predetermined frequency;

(b) a memory for storing the video signal inputted by said input means;

(c) phase variation detection means for detecting a phase variation in said signal of the predetermined frequency to produce an error signal related to the phase variation;

(d) interpolation means for generating an interpolation signal by using a plurality of error signals produced by said phase variation detection means which are successive along a time base; and

(e) readout control means for controlling the readout from said memory by using a difference between said interpolation signal and selected of said error signals.

10. A time base correcting device according to claim 9 wherein said readout control means includes a linear interpolation circuit for linearly interpolating the error signals adjacent along the time base and the interpolation signal.

11. A time base correcting device according to claim 10 wherein said linear interpolation circuit includes an integrator for integrating the differences between the error signals and the interpolation signal and reset means for resetting said integrator at said predetermined interval.

12. A time base correcting device according to claim 10 wherein said readout control means further includes a phase adjustment circuit for adjusting the phase of a clock of a predetermined frequency by the output of said linear interpolation circuit to produce a clock for controlling the readout of said memory.

13. A time base correcting device comprising:

(a) memory means for storing an input video signal including a signal of a predetermined frequency;

(b) phase variation detection means for detecting a phase variation in said signal of the predetermined frequency to produce an error signal related to the phase variation;

(c) interpolation means for generating an interpolation signal by using a plurality of error signals produced by said phase variation detection means which are adjacent along a time base; and

(d) readout control means controlling readout from said memory means by using a difference between said interpolation signal and at least one of said error signals.

14. A time base correcting device comprising:

(a) input means for inputting a video signal including a signal of a predetermined frequency;

(b) a memory for storing the video signal inputted by said input means;

(c) phase variation detection means for detecting a phase variation in said signal of the predetermined frequency to produce an error signal related to the phase variation;

(d) modifying means for generating a modified error signal by using at least three error signals produced by said phase variation detection means which are adjacent along a time base; and

(e) readout control means for controlling readout from said memory by using at least one of said three error signals and said modifier error signal.

15. A time base correcting device according to claim 14 wherein said modifying means includes a circuit for weight-adding at least three error signals.

16. A time base correcting device comprising:

(a) input means for inputting a video signal including a signal of a predetermined frequency;

(b) phase variation detection means for detecting a phase variation of said signal of the predetermined frequency to produce an error signal related to the phase variation;

(c) modifying means for generating a modified error signal by using at least three error signals produced by said phase variation detection means which are successive along a time base; and

(d) means for eliminating a time base variation of the video signal by using at least one of said three error signals and said modified error signal.

17. A time base correcting device comprising:

(a) input means for inputting a video signal including a sync. signal and a burst signal;

(b) means for generating a clock signal synchronized with the sync. signal of the video signal inputted by said input means;

(c) first phase comparison means for comparing phases of said burst signal and said clock signal at a predetermined interval to produce a first error signal;

(d) phase adjustment means for adjusting the phase of said clock in accordance with said first error signal;

(e) memory means for storing the video signal supplied from said input means in synchronism with said clock supplied through said phase adjustment means;

(f) controlled oscillation means;

(g) second phase comparison means for comparing the phases of the output of said controlled oscillation means and a signal of a predetermined frequency to produce a second error signal;

said second phase comparison means having substantially identical input/output characteristic to that of said first phase comparison means;

(h) adding means for adding a signal related to said first error signal and said second phase error signal and supplying the sum to said controlled oscillation means; and

(i) readout control means for controlling the readout from said memory means by the output signal of said controlled oscillation means.

18. A time base correcting device according to claim 17 further comprising linear interpolation means for linearly interpolating the first error signals adjacent along the time base.

19. A time base correcting device according to claim 18 wherein said linear interpolation means includes an integrator for integrating the differences between said first error signals and reset means for resetting said integrator at said predetermined interval.

20. A time base correcting device comprising:

(a) input means for inputting a video signal including a sync. signal of a predetermined frequency and a burst signal;

(b) means for generating a clock signal synchronized with the sync. signal of the video signal inputted by said input means;

(c) first phase comparison means for comparing phases of said burst signal and said clock signal to produce a first error signal;

(d) memory means for storing the video signal supplied from said input means in accordance with said first error signal;

(e) second comparison means for comparing phases of a signal having a frequency determined by said first error signal and a signal of a predetermined frequency to produce a second error signal;

said second comparison means having an input/output characteristic substantially identical to that of said first comparison means; and

(f) readout control means for controlling the readout from said memory by said second phase error signal.

21. A time base correcting device comprising:

(a) input means for inputting a video signal including a sync. signal and a burst signal;

(b) means for generating a clock signal synchronized with the sync. signal of the video signal inputted by said input means;

(c) first phase comparison means for comparing phases of said burst signal and said clock signal to produce a first error signal;

(d) second comparison means for comparing phases of a signal having a frequency determined by said first error signal and a signal of a predetermined frequency to produce a second error signal;

said second comparison means having an input/output characteristic substantially identical to that of said first comparison means; and

(e) means for eliminating a time base variation of the video signal by said first and second phase error signals.

22. A method for eliminating a time base variation in a cyclic video signal including a signal of a predetermined frequency, comprising the steps of:

(a) providing an error signal related to a phase variation of said signal of a predetermined frequency in a first cycle of said video signal;

(b) obtaining at least one further error signal related to a phase variation of said signal of a predetermined frequency in at least one successive cycle of said video signal; and

(c) eliminating said time base variation of the video signal by non-linear computation based on both said error signal and said further error signal.