Pointer processing circuit in sonet system

• US 5,335,223 A
• Filed: 12/18/1992
• Issued: 08/02/1994
• Est. Priority Date: 12/18/1991
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Iino, Hatsumi
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US07/998,571
• Time in Patent Office: 592 Days
• Field of Search: 370/58.1, 370/65.5, 370/84, 370/100.1, 370/105.1, 370/105.3, 370/105.4, 370/108, 375/106, 375/111, 375/114, 375/118, 375/119
• US Class Current: 370/503
• CPC Class Codes: H04J 3/0623 Synchronous multiplexing systems, e.g. synchronous digital hierarchy/synchronous optical network (SDH/SONET), synchronisation with a pointer process
• CPC Class Codes: H04L 2012/5674 Synchronisation, timing recovery or alignment
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections
• CPC Class Codes: Y10S 370/907 Synchronous optical network, SONET

Abstract

A pointer processing circuit which is incorporated in a SONET transmission apparatus having a cross connect equipment, is installed in the reception part of the cross connect equipment. The pointer processing circuit detects a phase difference between a multiplexed input frame signal for each input side transmission line, and receives a frame synchronous signal by which output frame signals are commonly synchronized. The frame synchronous signal is produced by a frame counter connected to the pointer processing circuit. The pointer processing circuit has a unit for adjusting a pointer value of the multiplexed input frame signal, based on the thus detected phase difference, before the cross connection of the input frame signals.

Claims

1. A pointer processing circuit in combination with a cross connect equipment in a SONET transmission system which has said cross connect equipment between a reception part and a transmission part, and a frame counter connected to said pointer processing circuit and producing a frame synchronous signal, wherein said reception part receives input frame signals from a plurality of input side transmission lines and applies said input frame signals to said cross connect equipment while said transmission part is provided with cross connected input frame signals from the cross connect equipment, reforms said cross connected frame signals into signals having a specified frame format and retransmits said signals as output frame signals to respective output side transmission lines in synchronism with said frame synchronous signal produced by said frame counter, the pointer processing circuit being installed in said reception part at said cross connect equipment so that pointer processing of said frame signals is carried out for every input side transmission line and each input frame signal has a pointer value before cross connection thereof, said pointer processing circuit comprising means to detect a phase difference between said input frame signal of each of said input side transmission lines and said frame synchronous signal from said frame counter and adjust the pointer value of said input frame signal for each of said input side transmission lines based on the thus detected phase difference signal so that the phase difference is cancelled.

2. A pointer processing circuit as set forth in claim 1, wherein said pointer processing circuit is comprised of a pointer adjusting unit and a frame comparating unit, both provided for each of said input side transmission lines, each of frame comparating units producing said phase difference between said input frame signal and said frame synchronous signal and each of pointer adjusting units receiving both said input frame signal and the phase difference signal from the corresponding frame comparating unit to adjust the pointer value of the thus received input frame signal in accordance with the value of said phase difference given as said phase difference signal.

3. A pointer processing circuit as set forth in claim 2, wherein each of said pointer adjusting units is comprised of a serial/parallel converter and a pointer inserter connected in series, said serial/parallel converter receives said input frame signal to achieve first a frame synchronization for the received input frame signal to generate a frame byte signal and then obtains a parallel frame signal, and said pointer inserter receives the parallel frame signal to adjust said pointer value, based on said phase difference signal, to input said pointer value to said cross connect equipment.

4. A pointer processing circuit as set forth in claim 3, wherein each of said frame comparating units is comprised of a frame comparator which receives said frame byte signal generated through said frame synchronization in said serial/parallel converter and also receives an output side frame byte signal, as said frame synchronous signal produced by said frame counter to produce said phase difference signal therefrom.

5. A pointer processing circuit as set forth in claim 4, wherein said frame comparator includes a flip-flop, an AND gate and a counter, connected in series in this order, said flip-flop receiving and being set by said frame byte signal from said serial/parallel converter and receiving and being reset by said output side frame byte signal from said frame counter and producing a resultant output which is applied to one of inputs of said AND gate which receives, at another input thereof, a payload clock given at every data signal transmission timing in each said frame signal, and said counter counting said payload clock passing through said AND gate.

6. A pointer processing circuit as set forth in claim 5, wherein said pointer inserter includes a buffer which receives said input frame signal to be written therein in accordance with a write payload clock supplied to said buffer, and outputs the written input frame signal therefrom in accordance with a read payload clock also supplied to said buffer in synchronism with a basic clock of said transmission system, a memory means which extracts an original pointer value from said input frame signal at the byte position of pointer bytes H1 and H2 and stores the original pointer value therein, an accumulator which adds said phase difference signal from said frame comparator with said original pointer value from said memory means to produce an adjusted pointer value according to said phase difference, and a gate means which allows the read frame signal from said buffer except for the pointer bytes to pass therethrough to said cross connect equipment and allows said adjusted pointer value from said accumulator to pass therethrough at every pointer byte position to said cross connect equipment.

7. A pointer processing circuit as set forth in claim 4, wherein said cross connect equipment is provided with a plurality of frame formers at an output thereof, each of said frame formers comprising a gate means which is operative to selectively insert a new overhead signal into the cross connected data signal output from said cross connect equipment at every point byte position specified by said frame counter to produce said output frame signals.

8. A pointer processing circuit as set forth in claim 7, wherein said frame counter includes at least a 1/8 divider receiving a basic clock of said transmission system, a 1/90 divider and 1/9 divider, connected in series in this order, and a decoder connected to and receiving output bits of said dividers, respectively, to produce overhead byte positions to said frame former.